3 of 12
RF5189
Rev A8 DS071212
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Pin
Function
Description
Interface Schematic
1RF IN
RF input. Input is matched to 50
Ω and DC block is provided internally.
2NC
No connect. Recommend connecting to ground.
3BIAS1GND
Ground for first stage bias circuit. For best performance, keep traces physi-
cally short and connect immediately to ground plane.
See pin 4.
4VREG1
First stage input bias. This pin requires a regulated supply to maintain
nominal bias current.
5VREG2
Second stage input bias. This pin requires a regulated supply to maintain
nominal bias current. Usually connected to VREG1.
See pin 4.
6BIAS2GND
Ground for second stage bias circuit. For best performance, connect to
ground with a choke inductor.
See pin 4.
7PWR SEN
Provides an output voltage proportional to output RF level.
8RF OUT
RF output. Output is matched to 50
Ω and DC block is provided internally.
9RF OUT
Same as pin 8.
See pin 8.
10
VCC2
Second stage output bias. Supply should be connected through a choke
inductor sized appropriately to handle the output bias current.
See pin 8.
11
VCC2
Same as pin 10.
See pin 8.
12
VCC1
First stage output bias. This pin is sensitive to bypass capacitors placed
close to it. Place an RF short approximately 200mils from this pin before
any other supply connections.
See pin 1.
Pkg
Base
GND
Ground connection. The backside of the package should be connected to
the ground plane through a short path (i.e., vias under the device will be
required).
INPUT
MATCH
VCC1
INTERSTAGE
MATCH
BIAS
VREG1
VREG2
BIAS
GND1
BIAS
GND2
RF OUT
OUTPUT
MATCH
VCC2
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