Combining Two Signals in ADC Applications

The CLC532 is applicable in a wide range of circuits and

applications. A classic example of this flexibility is combining

two or more signals for digitization by an analog-to-digital

converter (ADC). A clear understanding of both the multi-

plexer and the ADC’S operation is needed to optimize this

configuration.

To obtain the best performance from the combination, the

output of the CLC532 must be an accurate representation of

the selected input during the ADC conversion cycle. The

time at which the ADC saples the input varies with the type is

ADC that is being used.

Subranging ADCs usually have a Track-and-Hold (T/H) at

their input. For a successful combination of the multiplexer

and the ADC, the multiplexer timing and the T/H timing must

be compatible. When the ADC is given a converter com-

mand, the T/H transitions from all caps Track mode to all

caps Hold mode. The delay between the converter com-

mand and this transition is usually specified as Aperture

Delay or as Sampling Time Offset.

To maximize the time that the multiplexer output has to

settle, and that the T/H has to acquire the signal, the multi-

plexer should begin its transition from one input to the other

immediately after the T/H transition into HOLD mode. Unfor-

tunately it is during the initial portion of the HOLD period that

a subranging ADC performs analog processing of the

sampled signal. High slew rate transitions on the input during

this time may have a detrimental effect on the conversion

accuracy.

To minimize the effects of high input slew rates, one of two

strategies that can employed. Strategy one applies when the

sampling rate of the system is below the rated speed of the

ADC. For this case, the CLC532 SELECT timing is delayed

until after the multiplexer transition takes place, while the A/D

has completed one conversion cycle and is waiting for the

next convert command. As an example, if a CLC935

(15MSPS) ADC is being used at 10MSPS, the conversion

takes place in the first 67ns after the CONVERT command.

The next 33ns are spent waiting for the next CONVERT

command. This quite period would be an ideal place to

switch the multiplexer from one channel to the next.

Strategy two involves lowering the slew rate at the input of

the ADC so that less high frequency to feed through to the

hold capacitor during HOLD mode. The CLC532 output sig-

nal can be slew limited by increasing its compensation ca-

pacitors. This approach also has the advantage of limiting

the excess noise passed through the CLC532 to the ADC.

Figure 7 shows the recommended C

tion of ADC sample rate. Since the optimal values will

change from one ADC type to the next, this graph should be

used as a starting point for C

capacitors should be the same value to maintain output

symmetry.

Flash ADCs are similar to subranging ADCs in that the

sampling period is very brief. The primary difference is that

the acquisition time of a flash converter is much shorter than

that of a subranging ADC. It is only during this period that a

flash converter is susceptible to interference from a rapidly

changing analog input signal. With a flash ADC, the transi-

tion of the CLC532 output should be after the sampling

instant (”See timing diagram for ADC Aperture Delay” after

the CONVERT command).

Gain selection for an ADC

In many applications, such as RADAR, the dynamic range

requirements may exceed the accuracy requirements. Since

wide dynamic range ADC are also typically high accuracy

ADCs, this often leads the designer into wrongly selecting an

ADC which is a technical overkill and a budget buster. By

using the CLC532 as a selectable-gain stage, a less expen-

sive ADC can be used. As an example, if an application calls

for 80dB of dynamic Range and 0.05% accuracy, rather than

using a 14-bit converter, a 12-bit converter combined with

the circuit in

Figure 8 will meet the same objective. The

CLC532 is used to select between the analog input signal

and a version of the input signal attenuated by 12dB. The

circuit affords 14-bit dynamic range, 12-bit accuracy and

12-bit ease of implementation.

Sample Rate (MSPS)

10

11

12

13

14

15

16

17

18

19

20

50

45

40

35

30

25

20

15

10

5

DS012716-43

FIGURE 7. Recommend C

www.national.com

11