MLX90255 datasheet(3/5 Pages) MELEXIS

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MLX90255

Linear Optical Array

MLX90255 Linear Optical Array

Page 3 of 5

Rev 1.0 31-May-01

appropriate SI pulse to the optical array. The

required pull-down resistors are also foreseen

on the board. All important signals (SI, CLK,

VOUT, 5V and GND) are connected to test

terminals, which makes it easy to visualize them

on an oscilloscope. One sensor in a SMD

package is soldered on the PCB (called B) while

an external sensor can be connected to the 5-

pins connector row (upper right corner) (called

A). Both output signals are connected to test

terminals,

called

respectively

VOUTB

and

VOUTA.

An external regulated DC power supply, with an

output voltage between 6 and 10V, needs to be

connected to the screw connector in the upper

left corner of the PCB. A regular 9V battery is

also possible. (Mind the sign!) As soon as the

power supply is switched on, a LED lights up

and the micro controller starts generating the

CLK and SI signals with the selected frequency

and integration time.

The frequency of the signal CLK can be chosen

with the rotary DIL switch on the right. The

frequencies corresponding to the 16 positions of

this switch are shown in the following table.

Position

CLK frequency

36kHz

64kHz

77kHz

93kHz

112kHz

141kHz

170kHz

214kHz

284kHz

345kHz

435kHz

588kHz

909kHz

1.0MHz

1.25MHz

1.67MHz

Positions 0, E and F correspond to frequencies

that are outside the device specification. Lighting

up a second LED indicates selecting one of

them.

For

each

pulse,

133

CLK

pulses

are

generated with the selected frequency, and after

them the CLK line is pulled low until the next SI

pulse. See further in this document for the

correct timings.

The light integration time can be selected with

the other rotary DIL switch. Again 16 positions

are possible, however now there is no one-to-

one relation with the corresponding integration

times. Actually the switch specifies a time which

starts only after the 133

rd CLK pulse. As the

integration time already starts after the 18

th pulse

(see device specification), the total integration

time also depends on the selected frequency.

The following table shows for each position (of

the ‘integration time switch’) the minimal and the

maximal

integration

time,

corresponding

respectively the maximal and the minimal CLK

frequency.

Total Integration Time

Position

Minimal

Maximal

79us

3.17ms

230us

3.33ms

380us

3.48ms

682us

3.77ms

985us

4.09ms

1.30ms

4.40ms

2.50ms

5.60ms

3.10ms

6.20ms

3.85ms

6.95ms

4.60ms

7.70ms

6.10ms

9.15ms

7.7ms

10.7s

9.15ms

12.5ms

10.5ms

15ms

20ms

The analog output voltage is directly proportional

to the light intensity and the integration time up

to the devices saturation level (3V typical). The

response of a pixel can be described with the

following formula:

VOUT = PR*Plight + offset + PRerror*Plight + DC

where DC means the dark current.

The

proportionality

constant

the

responsivity

the

device

given

(V*cm2/µW*sec).

Responsivity

wavelength

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