133 MHz Spread Spectrum Clock Synthesizer/Driver

with AGP, USB, and DRCG Support

CY2210

Rev 1.0, November 25, 2006

Page 1 of 10

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555

Fax:(408) 855-0550

www.SpectraLinear.com

Y2210

Features

Benefits

• Mixed 2.5V and 3.3V Operation

(CY2210-2) synthesizer and driver specification

• Multiple output clocks at different frequencies

— Four CPU clocks, up to 133 MHz

— Eight synchronous PCI clocks, 1 free-running

— Two CPU/2 clocks, at one-half the CPU frequency

— Four AGP clocks at 66 MHz

— Three synchronous APIC clocks, at 16.67 MHz

— One USB clock at 48 MHz

— Two reference clocks at 14.318 MHz

Single-chip main motherboard clock generator

— Driven together, support 4 CPUs and a chipset

— Support for 4 PCI slots and chipset

— Drives up to two main memory clock generators, including

DRCG (CPUCLK/2)

— Support for multiple AGP slots

— Support multiprocessing systems

— Supports USB frequencies and I/O chip

• Spread Spectrum clocking

— 32.5-kHz modulation frequency @ 133 MHz

— 33.1-kHz modulation frequency @ 100 MHz for

CY2210-02/03

— 33.4-kHz modulation frequency @ 100 MHz for

CY2210-04

— EPROM programmable percentage of spreading. Default

is –0.6%, which is recommended by Intel

Enables reduction of EMI in some systems

• Power-down features

Supports mobile systems

• Three Select inputs

Supports up to eight CPU clock frequencies

• Low-skew and low-jitter outputs

Meets tight system timing requirements at high frequency

• OE and Test Mode support

Enables ATE and “bed of nails” testing

• 56-pin SSOP package

Widely available, standard package enables lower cost

Logic Block Diagram

EPROM

XTALOUT

XTALIN

APICCLK [0–2] (16.67 MHz)

14.318

MHz

OSC.

PCICLK_F (33.33 MHz)

SEL1

CPU

PLL

REFCLK [0–1] (14.318 MHz)

CPUCLK [0–3]

PCICLK [1–7] (33.33 MHz)

SYS

PLL

USBCLK (48 MHz)

CPU_STOP

PCI_STOP

SEL0

SEL133

CPUCLK/2 [0–1] (DRCG)

Divider,

EPRO

M-

PWR_DWN

AGPCLK [0–3] (66.67 MHz)

SPREAD

Top View

1

2

3

4

5

6

7

8

9

10

11

12

33

32

31

30

29

36

35

34

13

14

15

16

17

18

19

20

21

22

23

24

45

44

43

42

41

37

38

39

40

48

47

46

REFCLK0

REFCLK1

25

26

27

28

49

52

51

50

53

56

55

54

PCICLK6

SPREAD

APICCLK0

PCICLK5

AGPCLK3

PCI_STOP

CPUCLK/2

XTALIN

XTALOUT

PCICLK_F

PCICLK1

PCICLK2

PCICLK3

PCICLK4

PCICLK7

AGPCLK0

AGPCLK1

AGPCLK2

SEL1

SEL0

PWR_DWN

CPU_STOP

CPUCLK0

CPUCLK1

CPUCLK2

CPUCLK3

CPUCLK/2

APICCLK1

APICCLK2

SEL133

USBCLK

(DRCG)

(DRCG)

Pin Configuration