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CLC018 Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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CLC018 Datasheet(HTML) 10 Page - National Semiconductor (TI) |
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10 / 17 page ![]() Operation (Continued) TABLE 1. Interfacing of the Power Supplies and Bypass Capacitors Supply Operation Single −5V Single +5V Dual ±5V I/O Data Level ECL PECL ECL Control Signal Low/High −5V/GND GND/+5V GND/+5V Connection Key Information 1. Bypass each V EE supply with a 0.01 µF capacitor. 2. Connect V CC and VLL to the ground plane. 3. A power plane isn’t required for V EE but can be used. 1. Bypass each V CC supply with a 0.01 µF capacitor. 2. Bypass the V LL supply with a 0.01 µF. 3. Connect V EE to the ground plane. 4. Use a +5V power plane for V CC. 1. Bypass each V EE supply with a 0.01 µF capacitor. 2. Bypass the V LL supply with a 0.01 µF. 3. Connect V CC to the ground plane. 4. A power plane isn’t required for +5V (V LL) or −5V (VEE) supplies. but can be used. EXPANDING THE NUMBER OF OUTPUT PORTS To expand the number of output ports in a switch array, the inputs of multiple CLC018s are connected in parallel. The bus used to connect the input ports should be a controlled impedance transmission line as shown in Figure 11.To control the switch array, the IA, OA and TRI busses are all connected in parallel and a decoder is used to assert high the CS of the CLC018 that is to be addressed. This is also shown in Figure 11. www.national.com 10 |
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