MPF0900AMMA2ES datasheet(139/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

however, the internal clock must be set to the frequency closest to the expected input frequency to ensure

seamless transition to the internal clock, in the event a bad external frequency failure is present.

If the external clock is meant to start up after the PMIC has started up, the FSYNC pin must be maintained low

until the external clock is applied.

The FSYNC pin accepts frequencies in two selectable ranges as defined by the FSYNC_RANGE bit.

FSYNC_RANGE

FSYNC input frequency range

2.1 MHz to 2.8 MHz

333 kHz to 475 kHz

Table 187. FSYNC input frequency range selection bit

By default, the FSYNC_RANGE bit is reset to 1 at power up, and the MCU must set it to the desired operating

range after system startup and proceed to clear the FSYNC_FLT_I condition, to allow the PLL to generate the

switching frequency from the valid external frequency.

The FSYNC pin must receive a clock signal within the selected input range with a duty cycle between 41

% to 59 % to recognize it as a valid frequency. If the external clock is not present or invalid, the device will

automatically switch to the internal clock and set the FSYNC_FLT_I interrupt. The FSYNC_FLT_I will assert the

INTB pin if it is not masked.

The FSYNC_FLT_S bit is set to 1 as long as the frequency watchdog detects an invalid (out of range) input

frequency on the SYNC pin, and it will clear to 0 when the external frequency is back within the valid range.

The PF09 will switch back to the external switching frequency only when the FSYNC_FLT_I interrupt has been

cleared and the frequency watchdog is detecting a valid input frequency.

13.4.2.3 Electrical characteristics

All parameters are specified at TA = -40 °C to 125 °C, unless otherwise noted. Typical values are characterized at VIN = 5 V

and TA = 25 °C unless otherwise noted.

Symbol

Description

Min

Typ

Max

Unit

VFSYNC

FSYNC output voltage level

–

VDDIO

–

VOH_FSYNC

FSYNC output high voltage

• Minimum voltage at 2 mA load

VDDO-0.5

–

IOH_FSYNC

FSYNC output high current

–

VOL_FSYNC

FSYNC output low voltage

• Maximum voltage at 10 mA load

–

0.4

IOL_FSYNC

FSYNC output low current

–

FOUT_FSYNC

FSYNC output frequency

1.9

–

3.1

MHz

tPDLY_FSYNC

FSYNC propagation delay

–

VIH_FSYNC

FSYNC Input high voltage

• Minimum voltage to ensure a HIGH state

0.7*VDDIO

–

VIL_FSYNCOUT

FSYNC Input low voltage

• Maximum voltage to ensure a LOW state

–

0.4

IHYS_FSYNCOUT

FSYNC Input buffer hysteresis

100

–

400

IIN_LEAK_FSYNC

FSYNC input leakage

• Pin shorted to 5.5 V

–

μA

Table 188. FSYNC electrical characteristics

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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