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MPF0900AMMA2ES Datasheet(PDF) 185 Page - NXP Semiconductors |
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MPF0900AMMA2ES Datasheet(HTML) 185 Page - NXP Semiconductors |
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185 / 205 page  NXP Semiconductors PF09 Nine-channel power management IC with advanced system safety monitoring ADDR REGISTER DEFAULT BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 MSB OTP_SW4_ 2P5TH_HYS OTP_ SW4_LSEL OTP_SW4_UVTH[2:0] OTP_SW4_OVTH[2:0] 0x9F OTP_SW4_ CFG3 0000_0000 RW RW RW RW RW RW RW RW MSB OTP_SW4_ STBY_EN OTP_SW4_CCOMP[1:0] OTP_SW4_RCOMP[1:0] OTP_SW4_GM[2:0] 0xA0 OTP_SW4_ CFG4 0000_0000 RW RW RW RW RW RW RW RW MSB OTP_VSW5_RUN[7:0] 0xA1 OTP_SW5_ VRUN 0101_1001 RW RW RW RW RW RW RW RW MSB OTP_VSW5_STBY[7:0] 0xA2 OTP_SW5_ VSTBY 0101_1001 RW RW RW RW RW RW RW RW MSB — OTP_SW5_ILIM[1:0] OTP_SW5_DVS[1:0] OTP_SW5_PH[2:0] 0xA3 OTP_SW5_ CFG1 0000_0000 — RW RW RW RW RW RW RW MSB OTP_SW5_DVSMAX[3:0] OTP_SW5_DVSMIN[3:0] 0xA4 OTP_SW5_ CFG2 1111_1111 RW RW RW RW RW RW RW RW MSB OTP_SW5_ 2P5TH_HYS OTP_ SW5_LSEL OTP_SW5_UVTH[2:0] OTP_SW5_OVTH[2:0] 0xA5 OTP_SW5_ CFG3 0000_0000 RW RW RW RW RW RW RW RW MSB OTP_SW5_ STBY_EN OTP_SW5_CCOMP[1:0] OTP_SW5_RCOMP[1:0] OTP_SW5_GM[2:0] 0xA6 OTP_SW5_ CFG4 0000_0000 RW RW RW RW RW RW RW RW MSB OTP_ LDO1_SS — — OTP_VLDO1_RUN[4:0] 0xA7 OTP_ LDO1_RUN 0000_0000 RW — — RW RW RW RW RW MSB OTP_LDO1_ STBY_EN — — OTP_VLDO1_STBY[4:0] 0xA8 OTP_ LDO1_STBY 0000_0000 RW — — RW RW RW RW RW MSB OTP_LDO1LS — OTP_LDO1_UVTH[2:0] OTP_LDO1_OVTH[2:0] 0xA9 OTP_LDO1_ CFG1 0000_0000 RW — RW RW RW RW RW RW MSB OTP_ LDO2_SS — — OTP_VLDO2_RUN[4:0] 0xAA OTP_ LDO2_RUN 0000_0000 RW — — RW RW RW RW RW MSB OTP_LDO2_ STBY_EN — — OTP_VLDO2_STBY[4:0] 0xAB OTP_ LDO2_STBY 0000_0000 RW — — RW RW RW RW RW MSB OTP_LDO2_MODE[1:0] OTP_LDO2_UVTH[2:0] OTP_LDO2_OVTH[2:0] 0xAC OTP_LDO2_ CFG1 0000_0000 RW RW RW RW RW RW RW RW MSB OTP_ LDO3_SS — — OTP_VLDO3_RUN[4:0] 0xAD OTP_ LDO3_RUN 0000_0000 RW — — RW RW RW RW RW MSB OTP_LDO3_ STBY_EN — — OTP_VLDO3_STBY[4:0] 0xAE OTP_ LDO3_STBY 0000_0000 RW — — RW RW RW RW RW MSB OTP_LDO3_MODE[1:0] OTP_LDO3_UVTH[2:0] OTP_LDO3_OVTH[2:0] 0xAF OTP_LDO3_ CFG1 0000_0000 RW RW RW RW RW RW RW RW MSB OTP_VLDO3MON_TSET[1:0] OTP_VLDO3MON_TMASK[1:0] OTP_VLDO2MON_TSET[1:0] OTP_VLDO2MON_TMASK[1:0] 0xB0 OTP_ VLDOMON_ CFG 0000_0000 RW RW RW RW RW RW RW RW MSB — OTP_VAON_UVTH[1:0] — OTP_VAON_OVTH[1:0] OTP_VAON[1:0] 0xB1 OTP_VAON_ CFG1 0000_0000 — RW RW — RW RW RW RW MSB — — — — OTP_VAON_ FMODE OTP_VAON_TFLT[2:0] 0xB2 OTP_VAON_ CFG2 0000_0000 — — — — RW RW RW RW MSB — — — OTP_PROG_IDH[4:0] 0xB3 OTP_ PROG_IDH 0000_0000 — — — RW RW RW RW RW MSB — — OTP_PROG_IDL[5:0] 0xB4 OTP_ PROG_IDL 0000_0000 — — RW RW RW RW RW RW Table 232. OTP Register Map...continued PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback 185 / 205 |
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