CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *H
Page 12 of 19
Notes:
33. R/W must be HIGH during all address transitions.
34. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
35. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
36. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified tPWE.
37. To access RAM, CE = VIL, SEM = VIH.
38. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.
To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
39. Transition is measured
±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
40. During this period, the I/O pins are in the output state, and input signals must not be applied.
41. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Switching Waveforms (continued)
tAW
tWC
tPWE
tHD
tSD
tHA
CE
R/W
OE
DATA OUT
DATA IN
ADDRESS
tHZOE
tSA
tHZWE
tLZWE
Write Cycle No. 1: R/W Controlled Timing[33, 34, 35, 36]
[39]
[39]
[36]
[37, 38]
NOTE 40
NOTE 40
tAW
tWC
tSCE
tHD
tSD
tHA
CE
R/W
DATA IN
ADDRESS
tSA
Write Cycle No. 2: CE Controlled Timing[33, 34, 35, 41]
[37, 38]
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