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CY23FS04ZXCT Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY23FS04ZXCT
Description  Failsafe??2.5V/ 3.3V Zero Delay Buffer
PDF  12 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY23FS04ZXCT Datasheet(HTML) 1 Page - Cypress Semiconductor

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Failsafe™ 2.5V/ 3.3V Zero Delay Buffer
CY23FS04
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07304 Rev. *C
Revised June 8, 2005
Features
• Internal DCXO for continuous glitch-free operation
• Zero input-output propagation delay
• Low-jitter (< 35 ps RMS) outputs
• Low Output-to-Output skew (< 200 ps)
• 4.17 MHz–170 MHz reference input
• Supports industry standard input crystals
•170 MHz outputs
• 5V-tolerant inputs
• Phase-locked loop (PLL) Bypass Mode
• Dual Reference Inputs
• 16-pin TSSOP
• 2.5V or 3.3V output power supplies
• 3.3V core power supply
• Industrial temperature available
Functional Description
The CY23FS04 is a FailSafe
 zero delay buffer with two
reference clock inputs and four phase-aligned outputs. The
device provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure.
The continuous, glitch-free operation is achieved by using a
DCXO, which serves as a redundant clock source in the event
of a reference clock failure by maintaining the last frequency
and phase information of the reference clock.
The unique feature of the CY23FS04 is that the DCXO is in
fact the primary clocking source, which is synchronized
(phase-aligned) to the external reference clock. When this
external clock is restored, the DCXO automatically resynchro-
nizes to the external clock.
The frequency of the crystal, which will be connected to the
DCXO must be chosen to be an integer factor of the frequency
of the reference clock. This factor is set by two select lines:
S[2:1], please see Table 1. Output power supply, VDD can be
connected to either 2.5V or 3.3V. VDDC is the power supply
pin for internal circuits and must be connected to 3.3V.
Block Diagram
Pin Configuration
CLKA[1:2]
CLKB[1:2]
DCXO
Decoder
2
FailsafeTM
Block
PLL
XIN XOUT
2
2
REF2
FBK
S[2:1]
FAIL# /SAFE
REF1
REFSEL
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16 pin TSSOP
REF1
REF2
CLKB1
CLKB2
VSS
VDDC
XIN
S2
REFSEL
FBK
CLKA1
CLKA2
S1
VDD
FAIL#/SAFE
XOUT


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