C8051F360 datasheet(72/289 Pages) SILABS

72 / 289 page

C8051F360/1/2/3/4/5/6/7/8/9

Rev. 1.1

Figure 8.3. Comparator Hysteresis Plot

The Comparator hysteresis is software-programmable via the Comparator Control registers CPT0CN and

CPT1CN. The user can program both the amount of hysteresis voltage (referred to the input voltage) and

the positive and negative-going symmetry of this hysteresis around the threshold voltage.

The Comparator hysteresis is programmed using Bits3–0 in the Comparator Control registers CPT0CN

and CPT1CN (shown in SFR Definition 8.1 and SFR Definition 8.4). The amount of negative hysteresis

voltage is determined by the settings of the CP0HYN and CP1HYN bits. As shown in Figure 8.3, settings of

20, 10 or 5 mV of negative hysteresis can be programmed, or negative hysteresis can be disabled. In a

similar way, the amount of positive hysteresis is determined by the setting the CP0HYP and CP1HYP bits.

Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-

rupt enable and priority control, see Section “10. Interrupt Handler” on page 107). The CP0FIF or CP1FIF

flag is set to logic ‘1’ upon a Comparator falling-edge occurrence, and the CP0RIF or CP1RIF flag is set to

logic ‘1’ upon the Comparator rising-edge occurrence. Once set, these bits remain set until cleared by soft-

ware. The Comparator rising-edge interrupt mask is enabled by setting CP0RIE or CP1RIE to a logic ‘1’.

The Comparator falling-edge interrupt mask is enabled by setting CP0FIE or CP1FIE to a logic ‘1’.

The output state of the Comparator can be obtained at any time by reading the CP0OUT or CP1OUT bit.

The Comparator is enabled by setting the CP0EN or CP1EN bit to logic ‘1’, and is disabled by clearing this

bit to logic ‘0’.

Note that false rising edges and falling edges can be detected when the comparator is first powered on or

if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the

rising-edge and falling-edge flags be explicitly cleared to logic ‘0’ a short time after the comparator is

enabled or its mode bits have been changed. This Power Up Time is specified in Table 8.1 on page 79.

Positive Hysteresis Voltage

(Programmed with CP0HYP Bits)

Negative Hysteresis Voltage

(Programmed by CP0HYN Bits)

VIN-

VIN+

INPUTS

CIRCUIT CONFIGURATION

CP0+

CP0-

CP0

VIN+

VIN-

OUT

VOH

Positive Hysteresis

Disabled

Maximum

Positive Hysteresis

Negative Hysteresis

Disabled

Maximum

Negative Hysteresis

OUTPUT

VOL

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