CY28331
Document #: 38-07491 Rev. *E
Page 2 of 17
Pin Description
Pin
Name
PWR
I/O
Description
3XIN
VDD
I
Oscillator Buffer Input. Connect to a crystal or to an external clock.
4XOUT
VDD
O
Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at XIN.
41, 37
CPUT(0:1)
VDDC
O
CPU clock outputs 0 and 1: push-pull “true” output of differential pair.
40, 36
CPUC(0:1)
VDDC
O
CPU clock outputs 0 and 1: push-pull “complement” output of differential
pair.
13, 14, 17,
18, 21, 22
PCI33(0:5)
O
3.3V PCI clock outputs controlled by PCISTOP#.
23
PCISel /
PCI33_F
I/O
PCISel is a strap option during power-up to select Pin 24 functionality:
0: Configure Pin 24 as PCI33_6
1: Configure Pin 24 as PCISTOP# (default 100k internal pull-up)
After power-up, this pin reverts to standard PCI33_F output.
8, 11
PCI33_HT66(2:3)
VDDD
O
3.3V PCI 33-MHz or HyperTransport 66 clock outputs. This group is
selectable between 33 MHz and 66 MHz, based on the state of
PCI33HT66SEL[0:1]#.
6, 7
PCI33_HT66_[0:1]/
PCI33_HT66SEL[0:1]#
VDDD
I/O
PCI33 or HT66 select. This input strap selects the output frequency of
PCI33_HT66 outputs to either 33 MHz or 66 MHz. There is an internal
100Kohm pull-up resistor. After power-up, this pin becomes
PCI33_HT66_[0:1] output.
SEL1
SEL0
PIN6
PIN7
PIN8
PIN11
0
0
HT66_0
HT66_1
HT66_2
HT66_3
0
1
HT66_0
HT66_1
HT66_2
PCI33_3
1
0
HT66_0
HT66_1
PCI33_2
PCI33_3
1
1
HT66_0
PCI33_1 PCI33_2
PCI33_3
31
USB/FS3
I/O
3.3V USB clock output at 48 MHz. At power-up this pin is sensed to
determine the CPU output frequency. There is an internal 100K-ohm
pull-down resistor.
28
24_48MHz/SEL#
I/O
3.3V super I/O clock output. At power-up this pin is sensed to determine
whether the output is 24 MHz or 48 MHz. There is an internal 100K-ohm
pull-down resistor. This pin will be externally strapped high using a
10K-ohm resistor to VSS. 0 = 48 MHz, 1 = 24 MHz.
1, 48, 45
REF(0:2)/FS(0:2)
I/O
3.3V reference clock output. At power-up this pin is sensed to determine
the CPU output frequency. There is an internal 100K-ohm pull-up resistor
for FS0, while FS(1:2) includes 100K ohm pull-up resistors.
44
SRESET#/PD#
I/O
Watchdog Time-out Reset Output. Power-down input (100K internal
pull-up).
24
PCI33_6/
PCISTOP#
I/O
When configured through pin 23 as PCI_STOP#, this pin controls the
PCI33(0:5,7) and PCI33_HT66(1:3) outputs. Active LOW control input to
halt all 33-MHz PCI clocks except PCI33_F. Only the PCI33_HT66 outputs
that are running at 33 MHz will be stopped. The outputs will be glitch-free
when turning off and turning on (100K internal pull-up). When configured
through pin 23 as PCI33_6, PCI_STOP# is unavailable.
12
PCI33_7
O
3.3V PCI clock outputs controlled by PCISTOP#.
26
SDATA
I/O
Data pin for SMBus (rev2.0). There is an internal 100K-ohm pull-up
resistor.
25
SCLK
I
Clock pin for SMBus (rev2.0). There is an internal 100K-ohm pull-up
resistor.
2, 9, 16,
19, 29, 35,
38, 46
VDD
PWR Power connection to 3.3V for the core.
5, 10, 15,
20, 27, 30,
34, 39, 47
VSS
GND Power connection to GROUND for the CORE section of the chip.
43
VDDA
PWR Power connection to 3.3V for the ANALOG section of the chip.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
