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AVR32UC Datasheet(PDF) 6 Page - ATMEL Corporation |
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AVR32UC Datasheet(HTML) 6 Page - ATMEL Corporation |
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6 / 118 page  6 32002C–AVR32–11/07 AVR32 2. Programming Model This chapter describes the programming model and the set of registers accessible to the user. It also describes the implementation options in AVR32UC. 2.1 Architectural compatibility AVR32UC is fully compatible with the Atmel AVR32A architecture. 2.2 Implementation options 2.2.1 Memory protection AVR32UC optionally supports an MPU as specified by the AVR32 architecture. The chip integra- tor selects whether or not to implement the MPU. 2.2.2 Java support AVR32UC does not implement Java hardware acceleration. 2.3 Register file configuration The AVR32A architecture dictates a specific register file implementation, reproduced below. Figure 2-1. Register File in AVR32A 2.4 The Status Register The Status Register (SR) consists of two halfwords, one upper and one lower, see Figure 2-2 on page 7 and Figure 2-3 on page 7. The lower halfword contains the C, Z, N, V and Q flags, as well as the L and T bits, while the upper halfword contains information about the mode and state the processor executes in. The upper halfword can only be accessed from a privileged mode. Application Bit 0 Supervisor Bit 31 PC SR INT0PC FINTPC INT1PC SMPC R7 R5 R6 R4 R3 R1 R2 R0 Bit 0 Bit 31 PC SR R12 INT0PC FINTPC INT1PC SMPC R7 R5 R6 R4 R11 R9 R10 R8 R3 R1 R2 R0 INT0 SP_APP SP_SYS R12 R11 R9 R10 R8 Exception NMI INT1 INT2 INT3 LR LR Bit 0 Bit 31 PC SR R12 INT0PC FINTPC INT1PC SMPC R7 R5 R6 R4 R11 R9 R10 R8 R3 R1 R2 R0 SP_SYS LR Bit 0 Bit 31 PC SR R12 INT0PC FINTPC INT1PC SMPC R7 R5 R6 R4 R11 R9 R10 R8 R3 R1 R2 R0 SP_SYS LR Bit 0 Bit 31 PC SR R12 INT0PC FINTPC INT1PC SMPC R7 R5 R6 R4 R11 R9 R10 R8 R3 R1 R2 R0 SP_SYS LR Bit 0 Bit 31 PC SR R12 INT0PC FINTPC INT1PC SMPC R7 R5 R6 R4 R11 R9 R10 R8 R3 R1 R2 R0 SP_SYS LR Bit 0 Bit 31 PC SR R12 INT0PC FINTPC INT1PC SMPC R7 R5 R6 R4 R11 R9 R10 R8 R3 R1 R2 R0 SP_SYS LR Bit 0 Bit 31 PC SR R12 INT0PC FINTPC INT1PC SMPC R7 R5 R6 R4 R11 R9 R10 R8 R3 R1 R2 R0 SP_SYS LR |
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