Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

CY29774AI Datasheet(PDF) 2 Page - Cypress Semiconductor

Part # CY29774AI
Description  2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer
PDF  9 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY29774AI Datasheet(HTML) 2 Page - Cypress Semiconductor

  CY29774AI Datasheet HTML 1Page - Cypress Semiconductor CY29774AI Datasheet HTML 2Page - Cypress Semiconductor CY29774AI Datasheet HTML 3Page - Cypress Semiconductor CY29774AI Datasheet HTML 4Page - Cypress Semiconductor CY29774AI Datasheet HTML 5Page - Cypress Semiconductor CY29774AI Datasheet HTML 6Page - Cypress Semiconductor CY29774AI Datasheet HTML 7Page - Cypress Semiconductor CY29774AI Datasheet HTML 8Page - Cypress Semiconductor CY29774AI Datasheet HTML 9Page - Cypress Semiconductor  
Zoom Inzoom in Zoom Outzoom out
 2 / 9 page
background image
CY29774
Document #: 38-07479 Rev. **
Page 2 of 9
Notes:
1.
PU = Internal pull up, PD = Internal pull down
2.
A 0.1-
µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3.
AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply
pins.
Pin Description[1]
Pin
Name
I/O
Type
Description
9
TCLK0
I, PD
LVCMOS
LVCMOS/LVTTL reference clock input
10
TCLK1
I, PU
LVCMOS
LVCMOS/LVTTL reference clock input
16, 18, 21,
23, 25
QA(4:0)
O
LVCMOS
Clock output bank A
32, 34, 36,
38, 40
QB(4:0)
O
LVCMOS
Clock output bank B
44, 46, 48,
50
QC(3:0)
O
LVCMOS
Clock output bank C
29
FB_OUT
O
LVCMOS
Feedback clock output. Connect to FB_IN for normal operation.
31
FB_IN
I, PU
LVCMOS
Feedback clock input. Connect to FB_OUT for normal operation.
This input should be at the same voltage rail as input reference clock.
See Table 1.
2
MR#/OE
I, PU
LVCMOS
Output enable/disable input. See Table 2.
3CLK_STP#
I, PU
LVCMOS
Clock stop enable/disable input. See Table 2.
6
PLL_EN
I, PU
LVCMOS
PLL enable/disable input. See Table 2.
8
TCLK_SEL
I, PD
LVCMOS
Reference select input. See Table 2.
52
VCO_SEL
I, PD
LVCMOS
VCO divider select input. See Table 2.
7, 4, 5
SEL(A:C)
I, PD
LVCMOS
Frequency select input, Bank (A:C). See Table 3.
20, 14
FB_SEL(1,0)
I, PD
LVCMOS
Feedback dividers select input. See Table 4.
17, 22, 26
VDDQA
Supply
VDD
2.5V or 3.3V Power supply for bank A output clocks[2,3]
33, 37, 41
VDDQB
Supply
VDD
2.5V or 3.3V Power supply for bank B output clocks[2,3]
45, 49
VDDQC
Supply
VDD
2.5V or 3.3V Power supply for bank C output clocks[2,3]
28
VDDFB
Supply
VDD
2.5V or 3.3V Power supply for feedback output clock[2,3]
13
AVDD
Supply
VDD
2.5V or 3.3V Power supply for PLL[2,3]
12
VDD
Supply
VDD
2.5V or 3.3V Power supply for core and inputs[2,3]
15
AVSS
Supply
Ground
Analog Ground
1, 19, 24,
30, 35, 39,
43, 47, 51
VSS
Supply
Ground
Common Ground
11, 27, 42
NC
No Connection



Html Pages

1 2 3 4 5 6 7 8 9


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com