WM8956 datasheet(13/80 Pages) WOLFSON

13 / 80 page

Preliminary Technical Data

WM8956

PTD, July 2007, Rev 2.1

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, TA=+25

oC, Slave

Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

DACLRC propagation delay from BCLK falling edge

tDL

DACDAT setup time to BCLK rising edge

tDST

DACDAT hold time from BCLK rising edge

tDHT

AUDIO INTERFACE TIMING – SLAVE MODE

Figure 3 Digital Audio Data Timing – Slave Mode

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, TA=+25

oC, Slave

Mode, fs=48kHz,

MCLK= 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

tBCY

BCLK pulse width high

tBCH

BCLK pulse width low

tBCL

DACLRC set-up time to BCLK rising edge

tLRSU

DACLRC hold time from BCLK rising edge

tLRH

DACDAT hold time from BCLK rising edge

tDH

DACDAT set-up time to BCLK rising edge

tDS

Note:

BCLK period should always be greater than or equal to MCLK period.

WM8956 Datasheet(PDF) 13 Page - Wolfson Microelectronics plc

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