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TMS320C6000GDPA167 Datasheet(PDF) 97 Page - Texas Instruments |
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TMS320C6000GDPA167 Datasheet(HTML) 97 Page - Texas Instruments |
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97 / 148 page ![]() TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005 97 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over operating case temperature range (unless otherwise noted)† Supply voltage range, CVDD (see Note 2) −0.3 V to 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply voltage range, DVDD (see Note 2) −0.3 V to 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range −0.3 V to DVDD + 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage range −0.3 V to DVDD + 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating case temperature ranges, TC: (default) 0 _C to 90_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (A version) [GDPA-200, and PYPA-167] −40 _C to105_C . . . . . . Storage temperature range, Tstg −65 _C to 150_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 2: All voltage values are with respect to VSS. recommended operating conditions† MIN NOM MAX UNIT CVDD Supply voltage, Core referenced to VSS PYP packages only 1.14 1.20 1.32 V CVDD Supply voltage, Core referenced to VSS GDP packages only 1.14‡ 1.20‡ 1.32 V DVDD Supply voltage, I/O referenced to VSS 3.13 3.3 3.47 V VIH High-level input voltage All signals except CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET 2 V VIH High-level input voltage CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET 2 V VIL Low-level input voltage All signals except CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET 0.8 V VIL Low-level input voltage CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET 0.3*DVDD V IOH High-level output current§ All signals except ECLKOUT, CLKOUT2, CLKOUT3, CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 −8 mA OH ECLKOUT, CLKOUT2, and CLKOUT3 −16 mA I Low-level output current§ All signals except ECLKOUT, CLKOUT2, CLKOUT3, CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 8 mA IOL Low-level output current§ ECLKOUT, CLKOUT2, and CLKOUT3 16 mA CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 3 mA VOS Maximum voltage during overshoot (See Figure 25) 4¶ V VUS Maximum voltage during undershoot (See Figure 26) −0.7¶ V TC Operating case temperature Default 0 90 _C TC Operating case temperature A version (GDPA-200 and PYPA-167) –40 105 _C † The core supply should be powered up prior to (and powered down after), the I/O supply. Systems should be designed to ensure that neither supply is powered up for an extended period of time if the other supply is below the proper operating voltage. ‡ These values are compatible with existing 1.26−V designs. § Refers to DC (or steady state) currents only, actual switching currents are higher. For more details, see the device-specific IBIS models. ¶ The absolute maximum ratings should not be exceeded for more than 30% of the cycle period. |
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