AT25DF256 datasheet(24/47 Pages) RENESAS

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DS-AT25DF256-035 Rev.G

Page 24

2024-01-08

AT25DF256 Datasheet

11.1.7

RSTE Bit

The RSTE bit is used to enable or disable the Reset command. When the RSTE bit is in the Logical 0 state (the

default state after power-up), the Reset command is disabled and any attempts to reset the device using the

Reset command are ignored. When the RSTE bit is in the Logical 1 state, the Reset command is enabled.

The RSTE bit retains its state as long as power is applied to the device. Once set to the Logical 1 state, the RSTE

bit remains in that state until it is modified using the Write Status Register Byte 2 command or until the device has

been power cycled. The Reset command itself does not change the state of the RSTE bit.

1. Only bits 4 and 3 of Status Register Byte 2 are modified when using the Write Status Register Byte 2 command.

2. R/W = Readable and Writeable; R = Readable only.

Figure 18. Read Status Register

Table 7. Status Register Format – Byte 2

Bit(1)

Name

Type(2)

Description

RES

Reserved for future use

RES

Reserved for future use

RES

Reserved for future use

4RSTE

Reset Enabled

R/W

Reset command is disabled (default)

Reset command is enabled

RES

Reserved for future use

RES

Reserved for future use

RES

Reserved for future use

RDY/BSY

Ready/Busy Status

Device is ready

Device is busy with an internal operation

SCK

MSB

00000101

410 11

812

21 22

15 16

13 14

23 24

OPCODE

MSB

DDDDDD

MSB

DDDDDD

STATUS REGISTER BYTE1

STATUS REGISTER BYTE2

HIGH-IMPEDANCE

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