VDIP1 Vinculum VNC1L Prototyping Module

Datasheet Version 0.92

© Future Technology Devices Intl Ltd. 2006-2007

Page 

2.6SPIInterfaceSignalDescriptionsandTimingDiagrams

Ta�le 8 - Data and Control ��us �ignal Mode �ptions - �PI Inter�ace

Pin No.

Name

Type

Description

6

�CLK

Input

�PI Cloc� input�� 12MHz ma�imum.

8

�DI

Input

�PI �erial Data Input

9

�D�

�utput

�PI �erial Data �utput

10

C�

Input

�PI Chip �elect Input

Figure � - �PI �lave Data �ead Cycle

�PICLK

�PI Data In

�PI Data �ut

�PI C�

�/W �DD

D0

D1

D2

D�

D4

D�

D6

D7

1

1

0

From �tart - �PI C� must �e held high �or the entire read cycle�� and must �e ta�en low �or at least one cloc� period

�������h����������mpl�����Th�������b������I����I����h�R/Wb��-��pu����g�‘1�h�����ll���������b����������m

the chip. The ne�t �it is the address �it�� �DD�� which is used to indicate whether the data register (�0�) or the status

register (�1�) is read �rom. During the �PI read cycle a �yte o� data will start �eing output on �PI Data �ut on the ne�t

�l��k�y�l��������h���������b����M����������A������h�����h��b����l��k���u����h��h�p���h�����u�����I����

�ut should �e chec�ed to see i� the data read is new data. � �0� level here on �PI Data �ut means that the data read

is new data. � �1� indicates that the data read is old data�� and the read cycle should �e repeated to get new data.

�emem�er that C� must �e held low �or at least one cloc� period �e�ore �eing ta�en high again to continue with the

ne�t read or write cycle.

Figure 6 - �PI �lave Data Write Cycle

�PICLK

�PI Data In

�PI Data �ut

�PI C�

�/W �DD

D0

D1

D2

D�

D4

D�

D6

D7

1

0

0

From �tart - �PI C� must �e held high �or the entire write cycle�� and must �e ta�en low �or at least one cloc� period

�������h�����������mpl�����Th�������b������I����I����h�R/Wb��-��pu����g�‘0�h�����ll���������b���������

to the chip. The ne�t �it is the address �it�� �DD�� which is used to indicate whether the data register (�0�) or the status