| Electronic Components Datasheet Search |
|
TMS320DM641 Datasheet(PDF) 41 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TMS320DM641 Datasheet(HTML) 41 Page - Texas Instruments |
|
41 / 179 page ![]() Pin Assignments 41 June 2003 − Revised October 2005 SPRS222E VP1D[0]/CLKX1 VP1D[1]/FSX1 VP1D[2]/DX1 VP1D[3]/CLKS1 VP1D[4]/DR1 VP1D[5]/FSR1 VP1D[6]/CLKR1 VP1D[7] Capture/Display Buffer (2560 Bytes) VP1CLK0 VP1CLK1 VP1CTL0 VP1CTL1 VP1CTL2 Timing and Control Logic Video Port 1 (VP1) [DM641 only] Channel A† † Channel A supports: BT.656 (8-bit) display pipeline mode and BT.656 (8-bit) capture pipeline mode [TSI (8-bit) capture pipeline mode]. ‡ For DM641, the same STCLK signal is used for both video ports (VP0 and VP1). STCLK‡ Figure 1−6. Peripheral Signals (Continued) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |