SH7124 datasheet(49/782 Pages) RENESAS

Part #	SH7124

Description	Renesas 32-Bit RISC Microcomputer

PDF	782 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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49 / 782 page

Section 2

CPU

Rev. 3.00

Sep. 27, 2007

Page 29 of 758

REJ09B0243-0300

Addressing

Mode

Instruction

Format

Effective Address Calculation Method

Calculation

Formula

PC relative

Effective address is sum of PC and Rn.

+ Rn

PC + Rn

Immediate

#imm:8

8-bit immediate data imm of TST, AND, OR,

or XOR instruction is zero-extended.



#imm:8

8-bit immediate data imm of MOV, ADD, or

CMP/EQ instruction is sign-extended.



#imm:8

8-bit immediate data imm of TRAPA instruction

is zero-extended and multiplied by 4.



2.4.3

Instruction Formats

This section describes the instruction formats, and the meaning of the source and destination

operands. The meaning of the operands depends on the instruction code. The following symbols

are used in the table.

xxxx:

Instruction code

mmmm:

Source register

nnnn:

Destination register

iiii:

Immediate data

dddd:

Displacement

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