M40SZ100YMH datasheet(3/19 Pages) STMICROELECTRONICS

3 / 19 page

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M40SZ100Y, M40SZ100W

SUMMARY DESCRIPTION

The M40SZ100Y/W NVRAM Controller is a self-

contained device which converts a standard low-

power SRAM into a non-volatile memory. A preci-

sion voltage reference and comparator monitors

the VCC input for an out-of-tolerance condition.

When an invalid VCC condition occurs, the condi-

tioned chip enable output (ECON) is forced inactive

to write protect the stored data in the SRAM. Dur-

ing a power failure, the SRAM is switched from the

VCC pin to the lithium cell within the SNAPHAT (or

external battery for the 16-lead SOIC) to provide

the energy required for data retention. On a sub-

sequent power-up, the SRAM remains write pro-

tected until a valid power condition returns.

The 28-pin, 330 mil SOIC provides sockets with

gold plated contacts for direct connection to a sep-

arate SNAPHAT® housing containing the battery.

The SNAPHAT housing has gold plated pins

which mate with the sockets, ensuring reliable

connection. The housing is keyed to prevent im-

proper insertion. This unique design allows the

SNAPHAT battery package to be mounted on top

of the SOIC package after the completion of the

surface mount process which greatly reduces the

board manufacturing process complexity of either

directly soldering or inserting a battery into a sol-

dered holder. Providing non-volatility becomes a

“SNAP.” This feature is also available in the “top-

less” 16-pin SOIC package (MQ).

Insertion of the SNAPHAT housing after reflow

prevents potential battery damage due to the high

temperatures required for device surface-mount-

ing. The SNAPHAT housing is also keyed to pre-

vent reverse insertion.

The 28-pin SOIC and battery packages are

shipped separately in plastic anti-static tubes or in

Tape & Reel form. For the 28-lead SOIC, the bat-

tery/crystal package (e.g., SNAPHAT) part num-

ber is “M4ZXX-BR00SH” (see Table 13, page 17).

Caution: Do not place the SNAPHAT battery top

in conductive foam, as this will drain the lithium

button-cell battery.

Figure 3. Logic Diagram

Note: 1. For 16-pin SOIC package only.

Table 1. Signal Names

Note: 1. For SO16 only.

AI03933

VCC

M40SZ100Y

M40SZ100W

VSS

VOUT

PFI

ECON

PFO

RST

RSTIN

VBAT

(1)

Chip Enable Input

ECON

Conditioned Chip Enable Output

RST

Reset Output (Open Drain)

RSTIN

Reset Input

Battery Low Output (Open Drain)

VOUT

Supply Voltage Output

VCC

Supply Voltage

VBAT

(1)

Back-up Supply Voltage

PFI

Power Fail Input

PFO

Power Fail Output

VSS

Ground

Not Connected Internally

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