M48T128Y datasheet(8/22 Pages) STMICROELECTRONICS

8 / 22 page

M48T128Y, M48T128V*

8/22

WRITE Mode

The M48T128Y/V is in the WRITE Mode whenever

W (WRITE Enable) and E (Chip Enable) are low

state after the address inputs are stable.

The start of a WRITE is referenced from the latter

occurring falling edge of W or E. A WRITE is termi-

nated by the earlier rising edge of W or E. The ad-

dresses must be held valid throughout the cycle. E

or W must return high for a minimum of tEHAX from

Chip Enable or tWHAX from WRITE Enable prior to

the initiation of another READ or WRITE cycle.

Data-in must be valid tDVWH prior to the end of

WRITE and remain valid for tWHDX afterward. G

should be kept high during WRITE cycles to avoid

bus contention; although, if the output bus has

been activated by a low on E and G a low on W will

disable the outputs tWLQZ after W falls.

Figure 6. WRITE Enable Controlled, WRITE AC Waveform

Figure 7. Chip Enable Controlled, WRITE AC Waveforms

AI02382

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A16

DQ0-DQ7

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

AI02383

tAVAV

tEHAX

tDVEH

A0-A16

DQ0-DQ7

VALID

tAVEH

tAVEL

tAVWL

tELEH

tEHDX

DATA INPUT

M48T128Y Datasheet(PDF) 8 Page - STMicroelectronics

M48T128Y Datasheet(HTML) 8 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Datasheet Download

Link URL