MPD78C10AL datasheet(45/373 Pages) NEC

45 / 373 page

CHAPTER 2

PIN FUNCTIONS

µPD78C17/78C10A

These pins can be specified as an address bus (AB15 to AB8) corresponding to the size of the externally installed

device by means of the MODE0 and MODE1 pin settings, and the remaining pins can be used as general-purpose

input/output ports (see Table 2-3).

Table 2-3. Operation of PF7 to PF0 (

µPD78C17/78C10A)

MODE1

MODE0

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

External Address Space

Port

AB11

AB10

AB9

AB8

4K bytes

Port

AB13

AB12

AB11

AB10

AB9

AB8

16K bytes

Setting prohibited

AB15

AB14

AB13

AB12

AB11

AB10

AB9

AB8

63K/64K bytesNote

Note 63K (

µPD78C17), 64K (µPD78C10A)

In the reset state (RESET input=low) or in the hardware STOP mode (STOP input=low), pins PF7 to PF0 become

high-impedance. When the RESET input or STOP input subsequently returns to the high level, they are set as address

bus or port according to the status of the MODE1 and MODE0 pins.

Caution Emulation cannot be performed by an emulator for a program which varies the port F operating

mode dynamically. Therefore, once the mode has been set, it should not be changed to a different

mode.

2.1.6 WR (Write strobe) ... 3-state output

The strobe signal output for a write operation to external memory. This pin is driven high except in external memory

data write machine cycles. When the RESET signal is low or when in the hardware STOP mode, WR become high-

impedance.

Remark

In a data write to internal RAM, WR is driven high.

2.1.7 RD (Read strobe) ... 3-state output

The strobe signal output for a read operation on external memory. This pin is driven high except in external memory

data read machine cycles. When the RESET signal is low or when in the hardware STOP mode, RD become high-

impedance.

Remark

In a data read from internal ROM or RAM, RD is driven high.

2.1.8 ALE (Address latch enable) ... 3-state output

The strobe signal which externally latches the lower address information output to pins PD7 to PD0 for an access

to external memory. When the RESET signal is low or when in the hardware STOP mode, ALE is high-impedance.

Caution ALE output continues while the CPU is operating. Therefore, address latching by ALE is effective

external access machine cycles.

MPD78C10AL Datasheet(PDF) 45 Page - NEC

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