RN5VD

14

A

B

1

2

3

4

5

Detector Threshold Hysteresis

Released Voltage +VDET

Detected Voltage –VDET

Minimum Operaing Voltage

Delay Time

GND

GND

Supply Voltage

(VDD)

Output Voltage

(OUT)

OPERATION

Fig. 2 Operation Diagram

Fig. 1 Block Diagram

Step 1. Output voltage is equal to pull-up voltage.

Step 2. When input voltage (VDD) reaches the state of Vref

≥VDD · (Rb+Rc) /(Ra+Rb+Rc) at point A (Detected Voltage –VDET) , the output of comparator is

reversed, so that output voltage becomes GND. Discharging is performed from CD pin connected to an external capacitor. No delay time is generated.

Step 3.

Output voltage becomes indefinite when power source voltage(VDD) is smaller than minimum operating voltage. When the output is pulled up, VDD is

output.

Step 4. Output voltage becomes equal to GND.

Step 5. When input voltage (VDD) reaches the state of Vref

≤VDD · Rb/(Ra+Rb) at Point B (Released Voltage +VDET) , the output of comparator is reversed,

and the external capacitor is charged through CD pin, so that output voltage becomes equal to pulled-up voltage after a delay time

tD (=0.69

×106×CD) .

Step

Step 1

Step 2

Step 3

Step 4

Step 5

Comparator (–) Pin

Input Voltage

I

II

II

II

I

Comparator Output

LH

Indefinite

HL

Tr. 1, 2

OFF

ON

Indefinite

ON

OFF

Output Tr.

Nch

OFF

ON

Indefinite

ON

OFF

Pch

ON

OFF

Indefinite

OFF

ON

I.

Rb + Rc

Ra + Rb + Rc

· VDD

II.

Rb

Ra + Rb

· VDD

GND

OUT

CD

VDD

Ra

Current Source

Output Capacitor

RD

Rb

Rc

Tr.1

Tr.2

–

+

Comparator

Schmitt Trigger

Nch

Pch