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AM2434BSDFHIALVR.B Datasheet(PDF) 59 Page - Texas Instruments |
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AM2434BSDFHIALVR.B Datasheet(HTML) 59 Page - Texas Instruments |
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59 / 282 page  5.3.2 ADC MAIN Domain Instances Table 5-3. ADC0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] ADC0_REFN (5) (7) A ADC0 Negative Reference J16 ADC0_REFP (5) (6) A ADC0 Positive Reference J15 ADC0_AIN0 (2) (3) (4) A ADC Analog Input 0 / GPIO1_80 (Input Only) G20 H21 ADC0_AIN1 (2) (3) (4) A ADC Analog Input 1 / GPIO1_81 (Input Only) F20 F19 ADC0_AIN2 (2) (3) (4) A ADC Analog Input 2 / GPIO1_82 (Input Only) E21 F21 ADC0_AIN3 (2) (3) (4) A ADC Analog Input 3 / GPIO1_83 (Input Only) D20 F20 ADC0_AIN4 (2) (3) (4) A ADC Analog Input 4 / GPIO1_84 (Input Only) G21 H20 ADC0_AIN5 (2) (3) (4) A ADC Analog Input 5 / GPIO1_85 (Input Only) F21 E21 ADC0_AIN6 (2) (3) (4) A ADC Analog Input 6 / GPIO1_86 (Input Only) F19 G20 ADC0_AIN7 (2) (3) (4) A ADC Analog Input 7 / GPIO1_87 (Input Only) E20 E20 ADC_EXT_TRIGGER0 (1) I ADC Trigger Input B16, C13 B7, B9 ADC_EXT_TRIGGER1 (1) I ADC Trigger Input D14, D16 C11 (1) This ADC Trigger input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter. (2) The General Purpose Input signal associated with this ADC0_AIN input has a debounce function when ADC0 is configured to operate in GPI mode. For more information on configuring ADC0 to operate in GPI mode, see the TRM Analog-to-Digital Converter (ADC) section in the Peripherals chapter. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter. (3) The ADC0_AIN[7:0] inputs only have hysterisis when ADC0 is configured to operate in GPI mode. (4) Any unused ADC0_AIN inputs must be pulled to VSS through a resistor or connected directly to VSS when VDDA_ADC is connected to a power source. (5) The ADC0_REFP and ADC0_REFN reference inputs are analog inputs which must be treated like high transient power supply rails, where ADC0_REFN is expected to be connected directly to the PCB ground plane along with all other VSS pins, and ADC0_REFP is connected to a power source capable of providing at least 4mA of current. ADC0_REFP may be connected to the same power source as VDDA_ADC0 if the voltage tolerance of the supply provides an acceptable accuracy for the ADC reference. A high frequency decoupling capacitor must be connected directly between ADC0_REFP and ADC0_REFN. The high frequency decoupling capacitor should be placed in the ball array on the back side of the PCB and connected directly to the ADC0_REFP and ADC0_REFN pins with vias. ADC0_REFP may be connected to VSS if ADC0 is not used and VDDA_ADC0 has been connected to VSS. The high frequency decoupling capacitor described above will not be required if ADC0 is not used and ADC0_REFP is connected to VSS. See the Pin Connectivity Requirements section for more information on ADC0 connectivity. (6) ADC0_REFP is connected to VDDA_ADC0 inside the ALX packaged devices. (7) ADC0_REFN is connected to VSS inside the ALX packaged devices. 5.3.3 CPSW MAIN Domain Instances Table 5-4. CPSW3G0 RGMII1 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] RGMII1_RXC I RGMII Receive Clock AA5, W13 U1, Y13 RGMII1_RX_CTL I RGMII Receive Control V13, W6 U14, Y3 RGMII1_TXC IO RGMII Transmit Clock U14 W13 RGMII1_TX_CTL O RGMII Transmit Control U15 W16 RGMII1_RD0 I RGMII Receive Data 0 AA13, W5 AA11, T5 RGMII1_RD1 I RGMII Receive Data 1 U12, Y5 R2, W11 RGMII1_RD2 I RGMII Receive Data 2 V6, Y13 U2, Y15 RGMII1_RD3 I RGMII Receive Data 3 V12, V5 AA13, T1 RGMII1_TD0 O RGMII Transmit Data 0 V15 Y14 RGMII1_TD1 O RGMII Transmit Data 1 V14 Y16 RGMII1_TD2 O RGMII Transmit Data 2 W14 U13 RGMII1_TD3 O RGMII Transmit Data 3 AA14 AA14 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: AM2434 AM2432 AM2431 |
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