M54HCT139

M74HCT139

February 1993

DUAL 2 TO 4 DECODER/DEMULTIPLEXER

B1R

(Plastic Package)

ORDER CODES :

M54HCT139F1R

M74HCT139M1R

M74HCT139B1R

M74HCT139C1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

INPUT AND OUTPUT EQUIVALENT CIRCUIT

DESCRIPTION

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

COMPATIBLE WITH TTL OUTPUTS

.

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

BALANCED PROPAGATION DELAYS

.

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS139

The M54/74HCT139 is a high speed CMOS DUAL

TWO LINE TO FOUR LINE DECODER/DEMULTI-

PLEXER fabricated in silicon gate C2MOS technol-

ogy. It has the same high speed performance of

LSTTL combined with true CMOS low power con-

sumption. The active low enable input can be used for

gating or as a data input for demultiplexing applica-

tions. While the enable input is held high, all four out-

puts are high independently of the other inputs. All

inputs are equipped with protection circuits against

static discharge and transient excess volt-age.This in-

tegrated circuit has input and output characteristics

that are fully compatible with 54/74 LSTTL logic

families. M54/74HCT devices are designed to directly

interface HSC

components. They are also plug in replacements for

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