DIO1412

Version 1.0, Jul 2024

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© 2024 DIOO MICROCIRCUITS CO., LTD.

IV

13.2. DFN2*2-8(EP) ...................................................................................................................................... 30

13.3. DFN2*2-8 ............................................................................................................................................. 31

List of Figures

Figure 1. SMBus timing diagram ............................................................................................................................ 6

Figure 2. Internal temperature error vs. Ambient temperature ............................................................................... 7

Figure 3. External temperature error vs. External BJT temperature ...................................................................... 7

Figure 4. External temperature error vs. Ambient temperature ..............................................................................7

Figure 5. System design for DIO1412 .................................................................................................................. 13

Figure 6. Typical remote substrate transistor (e.g. CPU substrate PNP or 2N3906) ...........................................13

Figure 7. Typical remote discrete NPN transistor (e.g. 2N3904) ..........................................................................13

List of Tables

Table 1. Pin descriptions....................................................................................................................................................... 1

Table 2. Pin types................................................................................................................................................................... 2

Table 3. Conversion rate and current consumption........................................................................................................ 11

Table 4. Temperature data format......................................................................................................................................11

Table 5. SMBus (or I2C) address decode.........................................................................................................................12