R03DS0147EJ0200 Rev.2.00

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Feb.25.25

Datasheet

UPC812, UPC4092

High Stability, Low Offset Voltage

J-FET Input Dual Operational Amplifier

DESCRIPTION

UPC812, 4092 are unique J-FET input dual operational amplifiers that uses a high-speed PNP transistor (fT

=300 MHz) for the output stage to achieve fast response and high stability.

The resistor-trimming method proven in other Renesas High-Precision Op-Amp and High-Precision reference

voltage is incorporate in this Op-Amp input stage, thus producing an excellent low offset voltage characteristics

that has surpasses conventional general purpose op-amp in spite of being J-FET input.

Depending on the operating ambient temperature, UPC812 is suitable for communication application while

UPC4092 is for general-purpose usage.

In addition to this series of line-up, single channel type operational amplifier, UPC811 with the same circuit

configuration are also available.

FEATURES

• Input Offset Voltage

±1 mV (TYP.) ( ±3 mV MAX.)

• VIO Temperature Drift

±7 µV/°C (TYP.)

• Input Bias Current

50 pA (TYP.)

• Slew Rate

15 V/μs (TYP.)

• Unity Gain Frequency

4 MHz (TYP.))

• Input Equivalent Noise Voltage Density

19 nV/ Hz (TYP.) (f = 1 kHz)

• Stable operation against capacitive load

(Capacitive Load at 10000 pF, AV = +1 )

• Built-In Phase Compensation Circuit

• Built-In Output Short Circuit Protection

• Standard Dual Op-Amp terminal connection (pin compatible)

ORDERING INFORMATION

Order Name (1)

Package

UPC812G2-AP

8-Pin plastic SOP ( 5.72 mm ( 225 ))

UPC4092G2-AP

8-Pin plastic SOP ( 5.72 mm ( 225 ))

(1) Order names containing E1 or E2 indicate that the packaging format is embossed taping.

Pin 1 of E1 is on draw-out side, and pin 1 of E2 is at take-up side.