DIO6970

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DIO6970• Rev. 1.1

 

Layout Design

The layout design of DIO6970 regulator is relatively simple. For the best efficiency and minimum noise

problems, we should place the following components close to the IC: CIN, L, R1 and R2.

1) It is desirable to maximize the PCB copper area connecting to GND pin to achieve the best thermal and

noise performance. If the board space allowed, a ground plane is highly desirable.

2) CIN must be close to Pins IN and GND. The loop area formed by CIN and GND must be minimized.

3) The PCB copper area associated with SW pin must be minimized to avoid the potential noise problem.

4) The components R1 and R2, and the trace connecting to the FB pin must NOT be adjacent to the SW net

on the PCB layout to avoid the noise problem.

5) If the system chip interfacing with the EN pin has a high impedance state at shutdown mode and the IN pin

is connected directly to a power source such as a Li-Ion battery, it is desirable to add a pull down 1MΩ

resistor between the EN and GND pins to prevent the noise from falsely turning on the regulator at

shutdown mode.