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WM8991 Datasheet(PDF) 30 Page - Wolfson Microelectronics plc |
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WM8991 Datasheet(HTML) 30 Page - Wolfson Microelectronics plc |
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30 / 174 page ![]() WM8991 Pre-Production w PP, May 2008, Rev 3.1 30 AUDIO INTERFACE TIMING – MASTER MODE Figure 5 Digital Audio Data Timing - Master Mode (see Control Interface) Test Conditions DCVDD=1.8V, DBVDD=AVDD=3.3V, SPKVDD=5V, DGND=AGND=SPKGND=0V, TA=+25 oC, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Timing Information ADCLRC/ DACLRC (or DACLRC2) propagation delay from BCLK (or BCLK2) falling edge tDL 20 ns ADCDAT propagation delay from BCLK falling edge tDDA 20 ns DACDAT (or DACDAT2) setup time to BCLK rising edge tDST 20 ns DACDAT (or DACDAT2) hold time from BCLK rising edge tDHT 10 ns ADCLRC to ADCLRCB delay tDLRCB 10 ns |
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