TMS320DM6443 datasheet(2/223 Pages) TI

2 / 223 page

1.2 Description

TMS320DM6443

Digital Media System-on-Chip

SPRS282F – DECEMBER 2005 – REVISED MARCH 2008

www.ti.com

–

SmartMedia

• USB Port With Integrated 2.0 PHY

–

USB 2.0 High-/Full-Speed (480 Mbps) Client

• Enhanced Direct-Memory-Access (EDMA)

–

USB 2.0 High-/Full-/Low-Speed Host

Controller (64 Independent Channels)

(Mini-Host, Supporting One External

• Two 64-Bit General-Purpose Timers (Each

Device)

Configurable as Two 32-Bit Timers)

• Three Pulse Width Modulator (PWM) Outputs

• One 64-Bit Watch Dog Timer

• On-Chip ARM ROM Bootloader (RBL) to Boot

• Three UARTs (One with RTS and CTS Flow

From NAND Flash or UART

Control)

• ATA/ATAPI I/F (ATA/ATAPI-6 Specification)

• One Serial Peripheral Interface (SPI) with Two

• Individual Power-Saving Modes for ARM/DSP

Chip-Selects

• Flexible PLL Clock Generators

• Master/Slave Inter-Integrated Circuit (I2C

• IEEE-1149.1 (JTAG) Boundary-

Bus™)

Scan-Compatible

• Audio Serial Port (ASP)

• Up to 71 General-Purpose I/O (GPIO) Pins

–

I2S

(Multiplexed With Other Device Functions)

–

AC97 Audio Codec Interface

• 361-Pin Pb-Free BGA Package

–

Standard Voice Codec Interface (AIC12)

(ZWT Suffix), 0.8-mm Ball Pitch

• 10/100 Mb/s Ethernet MAC (EMAC)

• 0.09-µm/6-Level Cu Metal Process (CMOS)

–

IEEE 802.3 Compliant

–

Media Independent Interface (MII)

• 3.3-V and 1.8-V I/O, 1.2-V Internal

• VLYNQ™ Interface (FPGA Interface)

• Applications:

–

Digital Media

• Host-Port Interface (HPI) with 16-Bit

–

Networked Media Encode/Decode

Multiplexed Address/Data

–

Video Imaging

The TMS320DM6443 (also referenced as DM6443) leverages TI’s DaVinci™ technology to meet the

networked media encode and decode application processing needs of next-generation embedded devices.

The DM6443 enables OEMs and ODMs to quickly bring to market devices featuring robust operating

systems support, rich user interfaces, high processing performance, and long battery life through the

maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6443 provides benefits of both DSP and Reduced Instruction Set

Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an

ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and

processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and

memory system can operate continuously.

The ARM core incorporates:

• A coprocessor 15 (CP15) and protection module

• Data and program Memory Management Units (MMUs) with table look-aside buffers.

• Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual

index virtual tag (VIVT).

The

TMS320C64x+™

DSPs

are

the

highest-performance

fixed-point

DSP

generation

the

TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation

high-performance,

advanced

very-long-instruction-word

(VLIW)

architecture

developed

Texas

Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a

code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of

the C64x+ DSP with added functionality and an expanded instruction set.

Digital Media System-on-Chip (DMSoC)

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