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AS7261 − Detailed Descriptions

Interrupt Operation

If BANK is set to Mode 0 or Mode 1 then the data is ready after

the 1st integration time. If BANK is set to Mode 2 or Mode 3 then

the data is ready after two integration times. If the interrupt is

enabled (INT = 1) then when the data is ready, the INT line is

pulled low and DATA_RDY is set to 1. The INT line is released

(returns high) when the control register is read.

DATA_RDY is cleared to 0 when any of the sensor registers X, Y,

Z, NIR, D and C are read. For multi-byte sensor data (2 or 4 bytes),

after the 1st byte is read the remaining bytes are shadow

protected in case an integration cycle completes just after the

1st byte is read.

In continuous spectral conversion mode (BANK setting of Mode

0, 1, or 2), the sensors continue to gather information at the rate

of the integration time, hence if the sensor registers are not read

when the interrupt line goes low, it will stay low and the next

cycle’s sensor data will be available in the registers at the end

of the next integration cycle.

When the control register BANK bits are written with a value of

Mode 3, One-Shot Spectral Conversion mode is entered. When

a single set of contemporaneous sensor readings is desired,

writing BANK Mode 3 to the control register immediately

triggers exactly two spectral data conversion cycles. At the end

of these two conversion cycles, the DATA_RDY bit is set as for

the other BANK modes. To perform a new One-Shot sequence,

the control register BANK bits should be written with a value of

Mode 3 again. This process may continue until the user writes

a different value into the BANK bits.

I²C Slave Interface

If selected by the I2C_ENB pin setting, interface and control can

be accomplished through an I²C compatible slave interface to

a set of registers that provide access to device control functions

and output data. These registers on the AS7261 are, in reality,

implemented as virtual registers in software. The actual I²C

slave hardware registers number only three and are described

in the table below. The steps necessary to access the virtual

registers defined in the following are explained in pseudocode

for external I²C master writes and reads below.

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