AS7264N datasheet(22/42 Pages) AMSOSRAM

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ams Datasheet

Page 21

[v1-00] 2017-Oct-05

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AS7264N − Detailed Descriptions

Figure 20:

Power Mode Register

Figure 21:

Interrupt Pin Configuration Register

Figure 22:

Interrupt and Polling Clear Register

Figure 23:

Interrupt and Polling Enable Register

Addr: 0x04/0x84

PWR_MODE

Bit

Bit Name

Default

Access

Bit Description

7:2

RESV

R/W

Reserved, set to 000000 if writing the register

R/W

1= Normal Operation Power Mode

0= Low Power Mode

RSVD

R/W

Reserved, set to 0 if writing the register

Addr: 0x22

INTR_PIN_Config

Bit

Bit Name

Default

Access

Bit Description

7:0

INTR_PIN_Config

0x00

R/W

0x00 = INT pin disabled

0xCA = INT pin enabled

Addr: 0xF8

INTR_POLL_CLR

Bit

Bit Name

Default

Access

Bit Description

7:3

RESV

00000

R/W

Reserved, set to 00000 if writing the register

CLR

R/W

Set to 1 to clear any asserted interrupt pin INT (the

interrupt channel ready must be enabled). If the interrupt

channel ready is enabled this bit will read a 1.

1:0

RSVD

R/W

Reserved, set to 00 if writing the register

Addr: 0xF9

INT_POLL_EN

Bit

Bit Name

Default

Access

Bit Description

7:3

RESV

R/W

Reserved, set to 00000 if writing the register

2:1

R/W

Set to 1 to enable the channel data ready for polling or

interrupt.

RSVD

R/W

Reserved, set to 0 if writing the register

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