AS7341L-DLGT datasheet(50/65 Pages) AMSOSRAM

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AS7341L

Datasheet

• PUBLIC

DS000718

• v1-00 • 2020-May-25

│ 49

Figure 75:

CH4_DATA_H Register

Addr: 0x9E

CH4_DATA_H

Bit

Bit Name

Default

Access

Bit Description

7:0

CH4_DATA_H

CH4 ADC data

– high byte

CH5_DATA Register (Address 0x9F/0xA0)

Figure 76:

CH5_DATA_L Register

Addr: 0x9F

CH5_DATA_L

Bit

Bit Name

Default

Access

Bit Description

7:0

CH5_DATA_L

CH5 ADC data

– low byte

Figure 77:

CH5_DATA_H Register

Addr: 0xA0

CH5_DATA_H

Bit

Bit Name

Default

Access

Bit Description

7:0

CH5_DATA_H

CH5 ADC data

– high byte

10.2.8

Miscellaneous Configuration

CFG0 Register (Address 0xA9)

Figure 78:

CFG 0 Register

Addr: 0xA9

CFG0

Bit

Bit Name

Default

Access

Bit Description

7:6

reserved

LOW_POWER

Low Power Idle.

When asserted, the device will automatically run in a

low power mode whenever all functions are in wait

states or disabled.

AS7341L-DLGT Datasheet(PDF) 50 Page - ams-OSRAM AG

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