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CMV12000 Datasheet(PDF) 25 Page - ams-OSRAM AG

Part # CMV12000
Description  12Mp High Speed Machine Vision Global Shutter CMOS Image Sensor
PDF  85 Pages
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Manufacturer  AMSOSRAM [ams-OSRAM AG]
Direct Link  https://ams-osram.com/
Logo AMSOSRAM - ams-OSRAM AG

CMV12000 Datasheet(HTML) 25 Page - ams-OSRAM AG

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CMV12000
Functional Description
Datasheet
• PUBLIC
DS000603
• v6-00 • 2023-Sep-22
84
│ 24
7.2.7
SPI Programming
Programming the sensor is done by writing the appropriate values to the on-board registers. These
registers can be written over a simple serial interface (SPI). The details of the timing and data format
are described below. The data written to the programming registers can also be read out over this
same SPI interface.
SPI I/O’s are pulled low when not used/enabled.
SPI Write
The timing to write data over the SPI interface can be found below.
Figure 15:
SPI Write
The data is sampled by the device on the rising edge of the SPI_CLK and read-in at the last falling
SPI_CLK edge. The SPI_CLK has a maximum frequency of 30 MHz. The SPI_EN signal has to be
high for half a clock period before the first data bit is sampled. SPI_EN has to remain high for one
clock period after the last data bit is sampled.
One write action contains 24 data bits:
●
One control bit: First bit to be sent, indicates whether a read (‘0’) or write (‘1’) will occur on the
SPI interface.
●
7 address bits: These bits form the address of the programming register that needs to be
written. The address is sent MSB first.
●
16 data bits: These bits form the actual data that will be written in the register selected with the
address bits. The data is written MSB first.
When several sensor registers need to be written, the timing above can be repeated with SPI_EN
remaining high all the time. See the figure below for an example of 2 registers being written.
Figure 16:
SPI Write of Multiple Registers
SPI_EN
SPI_IN
SPI_CLK
C=
’1'
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
...
D3
D2
D1
D0
½ CLK
1 CLK
...
SPI_EN
SPI_IN
SPI_CLK
C=
’1'
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
...
D3
D2
D1
D0
C=
’1'
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
...
D3
D2
D1
D0
½ CLK
1 CLK
...
...



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