RZSLASHA3M datasheet(23/53 Pages) RENESAS

23 / 53 page

RZ/A3M Group Datasheet

Section 3. Electrical Characteristics

R01DS0482EJ0110

Rev.1.10

Page 23 of 53

Mar 31, 2025

3.5.2

SDHI Access Timing

3.5.2.1

SDHI Access Timing (SDR 3.3-V)

Table 3.16

SDHC AC Access Timing (SDR at 3.3-V Operation)

Default Speed Mode

(16.67 MHz)

High Speed Mode

(33.33 MHz)

Item

Symbol

Min.

Max.

Min.

Max.

Unit

Figures

SD_CLK clock cycle

tSDCYC

60.00

—

30.0

—

Figure 3.7

SD_CLK clock high level width

tSDWH

23.50

—

13.50

—

SD_CLK clock low level width

tSDWL

23.50

—

13.50

—

SD_CLK clock rise time

tSDLH

—

SD_CLK clock fall time

tSDHL

—

SD_CMD,SD_DATA output delay

tSDODLY

−4.50

4.0

−4.50

4.0

SD_CMD,SD_DATA input set up time

tSDIS

5.5

—

5.5

—

SD_CMD,SD_DATA input hold time

tSDIH

2.0

—

2.0

—

SD_CMD,SD_DATA input data width

tSDIDW

—

SD_CLK

(output)

SD_CMD/SD_DATA

(input)

tSDCYC

tSDWL

tSDWH

tSDIS

tSDIH

tSDODLY

(max)

tSDODLY

(min)

SD_CMD/SD_DATA

(output)

tSDIDW

tSDLH

tSDHL

Figure 3.7

SDHC Interface Timing (SDR 3.3-V Power Supply)

NOTE

The disclosure of other characteristics of the SD interface needs the conclusion of the following agreement.

● SD Host/Ancillary Product License Agreement (SD HALA)

For details, contact your local sales representatives.

RZ/A3M Datasheet(PDF) 23 Page - Renesas Technology Corp

RZ/A3M Datasheet(HTML) 23 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL