M89 FAMILY

6/7

ORDERING INFORMATION SCHEME

When delivered from ST, the FLASH+PSD device

has all bits in the memory and PLDs set to 1. The

FLASH+PSD Configuration Register bits are set to

0. The code, configuration, and PLD logic are

loaded

using

the

programming

procedure.

Information

for

programming

the

device

is

available directly from ST. Please contact your

local sales representative.

The notation used for the device number is as

shown in Table 6. For a list of available options

(speed, package, etc.) or for further information on

any aspect of this device, please see the full data

sheet (please consult our pages on the world wide

web:

www.st.com/flashpsd). Alternatively, please

contact your nearest ST Sales Office.

Table 6. Ordering Information Scheme

Note: 1. Available on the 4.5 to 5.5 V range, only.

Example:

M89 1 3 F 1 W –

15

T

1

T

SRAM Capacity

Option

1

16 Kbit

T

Tape & Reel Packing

3

64 Kbit

Temperature Range

Flash Memory Capacity

10 to 70

°C (commercial)

3

1 Mbit (128K x 8)

6

–40 to 85

°C (industrial)

4

2 Mbit (256K x 8)

2nd Non Volatile Memory

Package

1

256 Kbit EEPROM

K

PLCC52

2

256 Kbit Flash memory

T

PQFP52

Operating Voltage

Speed

Y

4.5 V to 5.5 V

-90

W

2.7 V to 3.6 V

-15

150 ns