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MK50H27PLCC Datasheet(PDF) 20 Page - STMicroelectronics

Part # MK50H27PLCC
Description  Signalling System 7 Link Controller
PDF  56 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

MK50H27PLCC Datasheet(HTML) 20 Page - STMicroelectronics

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the receipt of an MSU after having entered congestion. This primitive
indicates that the remote node congestion has abated.
4.1.2.3 Control and Status Register 2 (CSR2)
RAP<3:1> = 2
BIT
NAME
DESCRIPTION
15
CYCLE
Setting this bit selects a shorter DMA cycle (5 vs 6 SYSCLKs for bursting
or 5 vs 7 SYSCLKs for single DMA). See Figures 7a and 8a for details.
14
ESEN
Extended Scaler Enable. Setting this bit enables the use of the 16-bit
timer pre-scaler at IADR+24 rather than the 8-bit Scaler at IADR+02.
Using the 16-bit Scaler allows longer timer values at higher SYSCLK
rates. Set ESEN=0 for backward compatibility with the MK50H27.
13
0
Reserved, must be written as zeroes.
12
RSUTE
Received SU Timer Enable. Setting this bit enables a timer for detecting
more than 32xTP time between received Signal Units. If RSUTE=1,
PPRIM=5 will be issued upon expiry of the Received SU Timer. A typi-
cal use for RSUT is to detect breaking of the serial data connection.
11:09
0
Reserved, must be written as zeroes.
08
JSS7E
Japanese SS7 Enable. Setting this bit enables TTC JT-Q703 compliance.
When JSS7E=1 the MK50H27 will align using only SIEs, timers Tf, Ts,
To, Ta, and Te will be activated appropriately, and the SUERM will act
in accordance with JT-Q703 requiring interchanging the location of the
T and D fields in the Initialization Block.
If JSS7E=1 the MK50H27 will
NOT comply with all CCITT/ITU, ANSI, or AT&T specifications.
07:00
IADR
The high order 8 bits of the address of the first word (lowest address)
in the Initialization Block.
IADR
must
be written by the Host
prior to issuing an INIT primitive.
4.1.2.4 Control and Status Register 3 (CSR3)
RAP<3:1> = 3
BIT
NAME
DESCRIPTION
15:00
IADR
The low order 16 bits of the address of the first word (lowest address)
in the Initialization Block. Must be written by the Host prior to issu-
ing an INIT primitive. The Initialization block must begin on a word
boundary.
1
5
1
0
1
4
0
9
1
2
1
1
0
8
0
3
0
7
0
2
0
6
0
5
0
4
0
1
0
0
1
3
IADR<23:16>
0
000
C
Y
C
L
E
E
S
E
N
R
S
U
T
E
J
S
S
7
E
1
5
1
0
1
4
0
9
1
2
1
1
0
8
0
3
0
7
0
2
0
6
0
5
0
4
0
1
0
0
1
3
0
IADR <15:00>
MK50H27
20/56



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