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LP4054B5F Datasheet(PDF) 6 Page - Lowpower Semiconductor inc

Part # LP4054B5F
Description  500mA Standalone Linear Li-Ion Battery Charger
PDF  7 Pages
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Manufacturer  POWER [Lowpower Semiconductor inc]
Direct Link  http://www.lowpowersemi.com
Logo POWER - Lowpower Semiconductor inc

LP4054B5F Datasheet(HTML) 6 Page - Lowpower Semiconductor inc

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LP4054
Aug.-2017
Email: marketing@lowpowersemi.com
www.lowpowersemi.com
Page 6 of 7
Preliminary Datasheet
LP4054
Thermal Limit
An internal thermal feedback loop reduces the programmed
charge current if the die temperature attempts to rise above a
preset value of approximately 125℃. This feature protects the
LP4054 from excessive temperature and allows the user to
push the limits of the power handling capability of a given
circuit board without risk of damaging the LP4054. The charge
current can be set according to typical (not worst-case)
ambient temperature with the assurance that the charger will
automatically reduce the current in worst-case conditions.
Under voltage Lockout (UVLO)
An internal under voltage lockout circuit monitors the input
voltage and keeps the charger in shutdown mode until VIN
rises above the under voltage lockout threshold .The UVLO
circuit has a built-in hysteresis of 200mV. Furthermore, to
protect against reverse current in the power MOSFET, the
UVLO circuit keeps the charger in shutdown mode if VIN falls
to within 150mV of the battery voltage. If the UVLO
comparator is tripped, the charger will not come out of
shutdown mode until VIN raises 150mV above the battery
voltage.
Automatic Recharge
Once the charge cycle is terminated, the LP4054 continuously
monitors the voltage on the BAT pin using a comparator with
a 2ms filter time (TRECHARGE). A charge cycle restarts when the
battery voltage falls below 4.05V (which corresponds to
approximately 80% to 90% battery capacity). This ensures
that the battery is kept at or near a fully charged condition and
eliminates the need for periodic charge cycle initiations.
CHRG output enters a strong pull-down state during recharge
cycles.
Power Dissipation
The conditions that cause the LP4054 to reduce charge
current through thermal feedback can be approximated by
considering the power dissipated in the IC. Nearly all of this
power dissipation is generated by the internal MOSFET—this
is calculated to be approximately:
PD=(VIN-VBAT) × IBAT
Where PD is the power dissipated, VIN is the input supply
voltage, VBAT is the battery voltage and IBAT is the charge
current. The approximate ambient temperature at which the
thermal feedback begins to protect the IC is:
TA=125℃-PDθJA
TA=125℃-(VIN-VBAT)×IBAT×θJA
Example: An LP4054 operating from a 5V USB supply is
programmed to supply 300mA full-scale current to a
discharged Li-Ion battery with a voltage of 3.75V. Assuming
θJA is 250 ℃/W (see Board Layout Considerations), the
ambient temperature at which the LP4054 will begin to reduce
the charge current is approximately:
TA=125℃-(5V-3.75V)×(300mA)×250℃/W
TA=125℃-0.375W×250℃/W=31.25℃
Moreover, when thermal feedback reduces the charge current,
the voltage at the ISET pin is also reduced proportionally as
discussed in the Operation section. It is important to
remember that LP4054 applications do not need to be
designed for worst-case thermal conditions since the IC will
automatically reduce power dissipation when the junction
temperature reaches approximately 125℃.
VIN Bypass Capacitor
Many types of capacitors can be used for input bypassing;
however, caution must be exercised when using multilayer
ceramic capacitors. Because of the self-resonant and high Q
characteristics of some types of ceramic capacitors, high
voltage transients can be generated under some start-up
conditions, such as connecting the charger input to a live
power source. Adding a 1.5Ω resistor in series with an X5R
ceramic capacitor will minimize start-up voltage transients.
Layout Considerations
For the main current paths as indicated in bold lines,
keep their traces short and wide.
Put the input capacitor as close as possible to the device
pins (VIN and GND).
Connect all analog grounds to a command node and
then connect the command node to the power ground
behind the output capacitors.



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