9DB833

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

IDT®

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

5

9DB833

MAY 25, 2018

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the 9DB833. These ratings, which are standard

values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other

conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over

the recommended operating temperature range.

Electrical Characteristics–DIF_IN Clock Input Parameters

Electrical Characteristics–Current Consumption

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

3.3V Core Supply Voltage

VDDA/R

4.6

V

1,2

3.3V Logic Supply Voltage

VDD

4.6

V

1,2

Input Low Voltage

VIL

GND-0.5

V

1

Input High Voltage

VIH

Except for SMBus interface

VDD+0.5V

V

1

Input High Voltage

VIHSMB

SMBus clock and data pins

5.5V

V

1

Storage Temperature

Ts

-65

150

°C

1

Junction Temperature

Tj

125

°C

1

Input ESD protection

ESD prot

Human Body Model

2000

V

1

1Guaranteed by design and characterization, not 100% tested in production.

2 Operation under these conditions is neither implied nor guaranteed.

TAMB=TCOM or TIND unless otherwise indicated, supply voltages per normal operation conditions; see Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Input Crossover Voltage -

DIF_IN

VCROSS

Cross Over Voltage

150

375

900

mV

1

Input Swing - DIF_IN

VSWING

Differential value

300

mV

1

Input Slew Rate - DIF_IN

dv/dt

Measured differentially

0.6

8

V/ns

1,2

Input Leakage Current

IIN

VIN = VDD , VIN = GND

-5

5

uA

Input Duty Cycle

dtin

Measurement from differential waveform

45

55

%

1

Input Jitter - Cycle to Cycle

JDIFIn

Differential measurement

0

125

ps

1

1 Guaranteed by design and characterization, not 100% tested in production.

2 Slew rate measured through +/-75mV window centered around differential zero.

TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

Operating Supply Current

IDD3.3OP

All outputs active @100MHz, PLL Mode,

CL = Full load;

164

200

mA

1

IDD3.3PD

All diff pairs driven

53

60

mA

1

IDD3.3PDZ

All differential pairs tri-stated

3

6

mA

1

1Guaranteed by design and characterization, not 100% tested in production.

Powerdown Current