Rev B 11/16/15

3

PCI EXPRESSTM CLOCK GENERATOR

841S01 DATA SHEET

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer, a

two-signal serial interface is provided. Through the Serial Data

Interface, various device functions, such as individual clock output

buffers, can be individually enabled or disabled. The registers

associated with the Serial Data Interface initialize to their default

setting upon power-up, and therefore, use of this interface is optional.

Clock device register changes are normally made upon system

initialization, if any are required. The interface cannot be used during

system operation for power management functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read, block

write, and block read operations from the controller. For block

write/read operation, the bytes must be accessed in sequential order

from lowest to highest byte (most significant bit first) with the ability to

stop after any complete byte has been transferred. For byte write and

byte read operations, the system controller can access individually

indexed bytes. The offset of the indexed byte is encoded in the

command code, as described in Table 3A.

The block write and block read protocol is outlined in Table 3B, while

Table 3C outlines the corresponding byte write and byte read

protocol. The slave receiver address is 11010010 (D2h).

Table 3A.Command Code Definition

Table 3B. Block Read and Block Write Protocol

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation.

6:5

Chip select address, set to “00” to access device.

4:0

Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be “00000”.

Bit

Description = Block Write

Bit

Description = Block Read

1Start

1Start

2:8

Slave address - 7 bits

2:8

Slave address - 7 bits

9Write

9Write

10

Acknowledge from slave

10

Acknowledge from slave

11:18

Command Code - 8 bits

11:18

Command Code - 8 bits

19

Acknowledge from slave

19

Acknowledge from slave

20:27

Byte Count - 8 bits

20

Repeat start

28

Acknowledge from slave

21:27

Slave address - 7 bits

29:36

Data byte 1 - 8 bits

28

Read = 1

37

Acknowledge from slave

29

Acknowledge from slave

38:45

Data byte 2 - 8 bits

30:37

Byte Count from slave - 8 bits

46

Acknowledge from slave

38

Acknowledge

Data Byte/Slave Acknowledges

39:46

Data Byte 1 from slave - 8 bits

Data Byte N - 8 bits

47

Acknowledge

Acknowledge from slave

48:55

Data Byte 2 from slave - 8 bits

Stop

56

Acknowledge

Data Bytes from Slave/Acknowledge

Data Byte N from slave - 8 bits

Not Acknowledge