EM78P341 datasheet(16/102 Pages) EMC

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EM78P341N/342N/343N

8-Bit Microprocessor with OTP ROM

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Product Specification (V1.0) 12.01.2006

(This specification is subject to change without further notice)

6.1.4 R3 (Status Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RST

IOCS

Bit 7 (RST): Bit of reset type

Set to “1” if wake-up from sleep on pin change, comparator status

change, or AD conversion completed. Set to “0” if wake-up from other

reset types.

Bit 6 (IOCS): Select the Segment of IO control register

0 = Segment 0 (IOC50 ~ IOCF0) selected

1 = Segment 1 (IOC51 ~ IOCC1) selected

Bit 5:

Not used (reserved)

Bit 4 (T):

Time-out bit. Set to “1” by the "SLEP" and "WDTC" commands or during

power on, and reset to “0” by WDT time-out (see Section 6.5.2, The T

and P Status under Status Register for more details).

Bit 3 (P):

Power-down bit. Set to “1” during power-on or by a "WDTC" command

and reset to “0” by a "SLEP" command (see Section 6.5.2, The T and P

Status under Status Register for more details).

Bit 2 (Z):

Zero flag. Set to "1" if the result of an arithmetic or logic operation is

zero.

Bit 1 (DC):

Auxiliary carry flag

Bit 0 (C):

Carry flag

6.1.5 R4 (RAM Select Register)

Bit 7:

Set to “0” all the time

Bit 6:

Used to select Bank 0 or Bank 1 of register

Bits 5~0:

Used to select a register (address: 00~0F, 10~3F) in the indirect

addressing mode

See the table under Section 6.1.3.1, Data Memory Configuration.

EM78P341 Datasheet(PDF) 16 Page - ELAN Microelectronics Corp

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