74HC_HCT112

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© NXP Semiconductors N.V. 2016. All rights reserved.

Product data sheet

Rev. 3 — 9 August 2016

4 of 20

NXP Semiconductors

74HC112; 74HCT112

Dual JK flip-flop with set and reset; negative-edge trigger

6.

Functional description

[1]

If nSD and nRD simultaneously go from LOW-to-HIGH, the output states are unpredictable.

H = HIGH voltage level

h = HIGH voltage level one set-up time before the HIGH-to-LOW clock transition

L = LOW voltage level

l = LOW voltage level one set-up time before the HIGH-to-LOW clock transition

q = lowercase letters indicate the state of the referenced output one set-up time before the HIGH-to-LOW clock transition

X = don’t care

 = HIGH-to-LOW clock transition

7.

Limiting values

[1]

For SO16 packages: above 70

C, the value of P

tot derates linearly with 8 mW/K.

For (T)SSOP16 packages: above 60

C, the value of P

tot derates linearly with 5.5 mW/K.

Table 3.

Function selection[1]

Operating modes

Input

Output

nSD

nRD

nCP

nJ

nK

nQ

nQ

Asynchronous set

L

H

X

X

X

H

L

Asynchronous reset

H

L

X

X

X

L

H

Undetermined

L

L

X

X

X

H

L

Toggle

H

H



hh

q

q

Load 0 (reset)

H

H



lh

L

H

Load 1 (set)

H

H



hl

H

L

Hold no change

H

H



ll

q

q

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

VCC

supply voltage

0.5

+7

V

IIK

input clamping current

VI < 0.5 V or VI >VCC + 0.5 V

-

20

mA

IOK

output clamping current

VO < 0.5 V or VO >VCC +0.5 V

-

20

mA

IO

output current

0.5 V < V

O < VCC +0.5 V

-

25

mA

ICC

supply current

-

+50

mA

IGND

ground current

50

-

mA

Tstg

storage temperature

65

+150

C

Ptot

total power dissipation

SO16 and (T)SSOP16 packages

[1]

-500

mW