74LVC2G240

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© NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 8 — 8 April 2013

10 of 22

NXP Semiconductors

74LVC2G240

Dual inverting buffer/line driver; 3-state

Test data is given in Table 10.

Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig 9.

Test circuit for measuring switching times

VEXT

VCC

VI

VO

mna616

DUT

CL

RT

RL

RL

G

Table 10.

Test data

Supply voltage

Input

Load

VEXT

VI

CL

RL

tPLH, tPHL

tPZH, tPHZ

tPZL, tPLZ

1.65 V to 1.95 V

VCC

30 pF

1 k



open

GND

2

 V

CC

2.3 V to 2.7 V

VCC

30 pF

500



open

GND

2

 V

CC

2.7 V

2.7 V

50 pF

500



open

GND

6 V

3.0 V to 3.6 V

2.7 V

50 pF

500



open

GND

6 V

4.5 V to 5.5 V

VCC

50 pF

500



open

GND

2

 V

CC