74LVC74A

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© NXP B.V. 2012. All rights reserved.

Product data sheet

Rev. 7 — 20 November 2012

8 of 19

NXP Semiconductors

74LVC74A

Dual D-type flip-flop with set and reset; positive-edge trigger

[1]

Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.

[2]

tpd is the same as tPLH and tPHL.

[3]

Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4]

CPD is used to determine the dynamic power dissipation (PD in W).

PD =CPD  VCC2  fi  N+ (CL  VCC2  fo) where:

fi = input frequency in MHz; fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

(C

L  VCC

2

 f

o) = sum of the outputs

tsu

set-up time

nD to nCP; see Figure 7

VCC = 1.65 V to 1.95 V

3.0

-

-

3.0

-

ns

VCC = 2.3 V to 2.7 V

2.5

-

-

2.5

-

ns

VCC = 2.7 V

2.2

-

-

2.2

-

ns

VCC = 3.0 V to 3.6 V

2.0

0.8

-

2.0

-

ns

th

hold time

nD to nCP; see Figure 7

VCC = 1.65 V to 1.95 V

2.0

-

-

2.0

-

ns

VCC = 2.3 V to 2.7 V

1.5

-

-

1.5

-

ns

VCC = 2.7 V

1.0

-

-

1.0

-

ns

VCC = 3.0 V to 3.6 V

+1.0

0.2

-

1.0

-

ns

fmax

maximum

frequency

nCP; see Figure 7

VCC = 1.65 V to 1.95 V

100

-

-

80

-

MHz

VCC = 2.3 V to 2.7 V

125

-

-

100

-

MHz

VCC = 2.7 V

150

-

-

120

-

MHz

VCC = 3.0 V to 3.6 V

150

250

-

120

-

MHz

tsk(o)

output skew time VCC = 3.0 V to 3.6 V

[3]

-

-

1.0

-

1.5

ns

CPD

power

dissipation

capacitance

per flip-flop; VI =GND to VCC

[4]

VCC = 1.65 V to 1.95 V

-

12.4

-

-

-

pF

VCC = 2.3 V to 2.7 V

-

16.0

-

-

-

pF

VCC = 3.0 V to 3.6 V

-

19.1

-

-

-

pF

Table 8.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C Unit

Min

Typ[1]

Max

Min

Max