DSPIC30F2010 datasheet(89/204 Pages) MICROCHIP

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DS70118H-page 89

dsPIC30F2010

FIGURE 14-4:

DEAD-TIME TIMING DIAGRAM

14.8

Independent PWM Output

An independent PWM Output mode is required for

driving certain types of loads. A particular PWM output

pair is in the Independent Output mode when the

corresponding PMOD bit in the PWMCON1 register is

set. No dead-time control is implemented between

adjacent PWM I/O pins when the module is operating

in the Independent mode and both I/O pins are allowed

to be active simultaneously.

In the Independent mode, each duty cycle generator is

connected to both of the PWM I/O pins in an output

pair. By using the associated duty cycle register and

the appropriate bits in the OVDCON register, the user

may select the following signal output options for each

PWM I/O pin operating in the Independent mode:

• I/O pin outputs PWM signal

• I/O pin inactive

• I/O pin active

14.9

Single Pulse PWM Operation

The PWM module produces single pulse outputs when

the PTCON control bits PTMOD<1:0> = 10. Only

edge-aligned outputs may be produced in the Single

Pulse mode. In Single Pulse mode, the PWM I/O pin(s)

are driven to the active state when the PTEN bit is set.

When a match with a duty cycle register occurs, the

PWM I/O pin is driven to the inactive state. When a

match with the PTPER register occurs, the PTMR reg-

ister is cleared, all active PWM I/O pins are driven to

the inactive state, the PTEN bit is cleared, and an

interrupt is generated.

14.10 PWM Output Override

The PWM output override bits allow the user to

manually drive the PWM I/O pins to specified logic

states, independent of the duty cycle comparison units.

All control bits associated with the PWM output

override function are contained in the OVDCON

contains six bits, POVDxH<3:1> and POVDxL<3:1>,

that determine which PWM I/O pins will be overridden.

The lower half of the OVDCON register contains six

bits, POUTxH<3:1> and POUTxL<3:1>, that determine

the state of the PWM I/O pins when a particular output

is overridden via the POVD bits.

14.10.1

COMPLEMENTARY OUTPUT MODE

When a PWMxL pin is driven active via the OVDCON

complement of the corresponding PWMxH pin in the

pair. Dead-time insertion is still performed when PWM

channels are overridden manually.

14.10.2

OVERRIDE SYNCHRONIZATION

If the OSYNC bit in the PWMCON2 register is set, all

output overrides performed via the OVDCON register

are synchronized to the PWM time base. Synchronous

output overrides occur at the following times:

• Edge-Aligned mode, when PTMR is zero.

• Center-Aligned modes, when PTMR is zero and

when the value of PTMR matches PTPER.

Duty Cycle Generator

PWMxH

PWMxL

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