CY54FCT543T, CY74FCT543T

8-BIT LATCHED REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCCS030A – MAY 1994 – REVISED OCTOBER 2001

2

POST OFFICE BOX 655303

PIN DESCRIPTION

NAME

DESCRIPTION

OEAB

A-to-B output-enable input (active low)

OEBA

B-to-A output-enable input (active low)

CEAB

A-to-B enable input (active low)

CEBA

B-to-A enable input (active low)

LEAB

A-to-B latch-enable input (active low)

LEBA

B-to-A latch-enable input (active low)

A

A-to-B data inputs or B-to-A 3-state outputs

B

B-to-A data inputs or A-to-B 3-state outputs

ORDERING INFORMATION

TA

PACKAGE†

SPEED

(ns)

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QSOP – Q

Tape and reel

5.3

CY74FCT543CTQCT

FCT543C

SOIC

SO

Tube

5.3

CY74FCT543CTSOC

FCT543C

SOIC – SO

Tape and reel

5.3

CY74FCT543CTSOCT

FCT543C

QSOP – Q

Tape and reel

6.5

CY74FCT543ATQCT

FCT543A

–40

°C to 85°C

SOIC

SO

Tube

6.5

CY74FCT543ATSOC

FCT543A

SOIC – SO

Tape and reel

6.5

CY74FCT543ATSOCT

FCT543A

QSOP – Q

Tape and reel

8.5

CY74FCT543TQCT

FCT543

SOIC

SO

Tube

8.5

CY74FCT543TSOC

FCT543

SOIC – SO

Tape and reel

8.5

CY74FCT543TSOCT

FCT543

55

°Cto125°C

CDIP

D

Tube

10

CY54FCT543TDMB

–55

°C to 125°C

CDIP – D

Tube

10

CY54FCT543TLMB

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE‡

INPUTS

LATCH

OUTPUT

CEAB

LEAB

OEAB

A TO B§

B

H

X

X

Storing

Z

X

H

X

Storing

X

X

XH

X

Z

L

L

L

Transparent

Current A inputs

L

H

L

Storing

Previous A inputs

H = High logic level, L = Low logic level, X = Don’t care,

Z = High-impedance state

‡ A-to-B data flow shown; B-to-A flow control is the same, except uses

CEBA, LEBA, and OEBA.

§ Before LEAB low-to-high transition