STA001

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FUNCTIONAL DESCRIPTION

Receiver chain

The receiver chain transforms the RF frequency signals to an IF signal at 1.84 MHz Carrier directly usable by

the Channel decoder.

In front of the STA001 IC it can be placed an external LNA and a bandpass filter; the bandpass filter limitates

the input bandwidth and guarantees a suitable rejection to the image frequency.

The STA001 input stage is a LNA working in the 1452-1492 MHz band. The RF signal is downconverted, using

an active mixer, to a first IF of 115.244 MHz. The first LO is tunable with a frequency step of 460 KHz.

The RF can be reduced 5dB by an external trimmer/resistor connected between PADJ1 and PADJ2 pins.

An IF variable gain amplifier guarantees 54 dB typical of gain range.

Using pins GADJ1, GADJ2, the output RX signal level can be decreased to the desired value by an external

trimmer/resistor.

Moreover, the IF chain can be configured to have a fixed gain by fixing statically control voltages on AGC1 and

AGC2 pins (i.e. V(AGC1)=VCC and V(AGC2)=GND), and by trimming the gain through connecting an external

resistor between GADJ1 and GADJ2.

By using an 800 Ohm resistor connected between GADJ1 and GADJ2, for example, a typical 56 dBs IF static

gain is obtained.

The first IF signal, having a bandwidth of 2.5 MHz, shaped by an external SAW filter, is downconverted to a

second IF of 1.84 MHz.

A differential clock output at 14.72 MHz is available to be used from the baseband.

Synthesizers, PLL, charge pump and VCOs

The first Voltage controlled Oscillator is controlled by an integrated PLL and it's able to cover a frequency range

of 37MHz with a step size of 460 KHz.

The second Voltage controlled oscillator produces a fixed 117.08MHz frequency controlled by a second inte-

grated PLL. Moreover, the 2nd PLL is able to select 2 other fixed frequencies, i.e. 111.76MHz and 122.4MHz,

suitable for application test.

The other components of the first PLL synthesizer are a low frequency programmable divider and a dual mod-

ulus prescaler; a fixed dividers is instead used to synthesize the second VCO frequency. Other fixed internal

dividers are used to get the comparation frequencies of both loops.

µP.

POWER SUPPLIES

The chip operates from an unregulated power supply of 2.7 to 3.3 Volts. All interface circuits to the baseband

chips are operating between these supplies unless otherwise specified.

INTERFACE SPECIFICATION

All the interface voltage levels to the micro controller are referenced to the supply voltage of the interface power

supply (GND) . The interface voltage levels are therefore fully compatible with the base band circuits.

The digital levels are all CMOS threshold compatible with the exception of M_CLK1, M_CLK2 pins (ECL type).

For completeness all other interface signals are also included.

of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected to SDA and SCL).