STA014T datasheet(13/45 Pages) STMICROELECTRONICS

13 / 45 page

5.1.2 - Stop condition

STOP is identified by low to high transition of the

data bus SDA signal while the clock signal SCL is

stable in the high state. A STOP condition termi-

nates communications between STA014 and the

bus master.

5.1.3 - Acknowledge bit

An acknowledge bit is used to indicate a success-

ful data transfer. The bus transmitter, either mas-

ter or slave, releases the SDA bus after sending

8 bit of data.

During the 9th clock pulse the receiver pulls the

SDA bus low to acknowledge the receipt of 8 bits

of data.

5.1.4 - Data input

During the data input the STA014 samples the

SDA signal on the rising edge of the clock SCL.

For correct device operation the SDA signal has

to be stable during the rising edge of the clock

and the data can change only when the SCL line

is low.

5.2 - DEVICE ADDRESSING

To start communication between the master and

the STA014, the master must initiate with a start

condition. Following this, the master sends onto

the SDA line 8 bits (MSB first) corresponding to

the device select address and read or write

mode.

The 7 most significant bits are the device address

identifier, corresponding to the I

2C bus definition.

For the STA014 these are fixed as 1000011.

The 8th bit (LSB) is the read or write operation

RW, this bit is set to 1 in read mode and 0 for

write mode. After a START condition the STA014

identifies on the bus the device address and, if a

match is found, it acknowledges the identification

on SDA bus during the 9th bit time. The following

byte after the device identification byte is the in-

ternal space address.

5.3 - WRITE OPERATION (see fig. 16)

Following a START condition the master sends a

device select code with the RW bit set to 0.

The STA014 acknowledges this and waits for the

byte of internal address.

After receiving the internal bytes address the

STA014 again responds with an acknowledge.

5.3.1 - Byte write

In the byte write mode the master sends one data

byte, this is acknowledged by STA014. The mas-

ter then terminates the transfer by generating a

STOP condition.

5.3.2 - Multibyte write

The multibyte write mode can start from any inter-

nal address.

The transfer is terminated by the

master generating a STOP condition.

DEV-ADDR

ACK

START

D98AU826A

DATA

NO ACK

STOP

CURRENT

ADDRESS

READ

DEV-ADDR

ACK

START

SUB-ADDR

ACK

DEV-ADDR

ACK

STOP

RANDOM

ADDRESS

READ

DATA

NO ACK

START

DEV-ADDR

ACK

START

DATA

ACK

DATA

ACK

STOP

SEQUENTIAL

CURRENT

READ

DATA

NO ACK

DEV-ADDR

ACK

START

SUB-ADDR

ACK

DEV-ADDR

ACK

SEQUENTIAL

RANDOM

READ

DATA

ACK

START

DATA

ACK

NO ACK

STOP

DATA

RW=

HIGH

Figure 17. Read Mode Sequence

DEV-ADDR

ACK

START

D98AU825B

SUB-ADDR

ACK

DATA IN

ACK

STOP

BYTE

WRITE

DEV-ADDR

ACK

START

SUB-ADDR

ACK

DATA IN

ACK

STOP

MULTIBYTE

WRITE

DATA IN

ACK

Figure 16. Write Mode Sequence

STA014-STA014B-STA014T

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