MIC44F19YML datasheet(12/13 Pages) MICREL

12 / 13 page

Micrel, Inc.

MIC44F18/19/20

January 2007

M9999-011207

Propagation Delay and Delay Matching and Other

Timing Considerations

Fast propagation delay between the input and output drive

waveform is desirable. It improves overcurrent protection

by decreasing the response time between the control

signal

and

the

MOSFET

gate

drive.

Minimizing

propagation delay also minimizes phase shift errors in

power supplies with wide bandwidth control loops.

Care must be taken to insure the input signal pulse width

is greater than the minimum specified pulse width. An

input signal that is less than the minimum pulse width may

result in no output pulse or an output pulse whose width is

significantly less than the input.

Decoupling and Bootstrap Capacitor Selection

Decoupling capacitors are required for proper operation by

supplying the charge necessary to drive the external

MOSFETs as well as minimizing the voltage ripple on the

supply pins.

Ceramic capacitors are recommended because of their

low impedance and small size. Z5U type ceramic capacitor

dielectrics are not recommended due to the large change

in capacitance over temperature and voltage. A minimum

value of 0.1µf is required for each of the capacitors,

regardless of the MOSFETs being driven. Larger

MOSFETs may require larger capacitance values for

proper operation. The voltage rating of the capacitors

depends upon the supply voltage, ambient temperature

and the voltage derating used for reliability.

Placement of the decoupling capacitors is critical. The

bypass capacitor for VDD should be placed as close as

possible between the VDD and VSS pins. The etch

connections must be short, wide and direct. The use of a

ground plane to minimize connection impedance is

recommended. Refer to the section on layout and

component placement for more information.

Grounding, Component Placement and Circuit Layout

Nanosecond switching speeds and ampere peak currents

in and around the MOSFET driver requires proper

placement and trace routing of all components. Improper

placement may cause degraded noise immunity, false

switching and excessive ringing.

Figure 7 shows the critical current paths when the driver

outputs go high and turn on the external MOSFETs. It also

helps demonstrate the need for a low impedance ground

plane. Charge needed to turn-on the MOSFET gates

comes from the decoupling capacitors CVDD. Current in the

gate driver flows from CVDD through the internal driver, into

the MOSFET gate and out the source. The return

connection back to the decoupling capacitor is made

through the ground plane. Any inductance or resistance in

the ground return path causes a voltage spike or ringing to

appear on the source of the MOSFET. This voltage works

against the gate drive voltage and can either slow down or

turn off the MOSFET during the period when it should be

turned on.

Figure 7. Critical Current Paths for High Driver

Outputs

Figure 8 shows the critical current paths when the driver

outputs go low and turn off the external MOSFETs. Short,

low impedance connections are important during turn-off

for the same reasons given in the turn-on explanation.

Current from the VDD supply replenishes charge in the

decoupling capacitor, CVdd.

Figure 8. Critical Current Paths for High Driver

Outputs

The following circuit guidelines should be adhered to for

optimum circuit performance:

1. The VCC bypass capacitor must be placed close to

the VDD and ground pins. It is critical that the etch

length between the decoupling capacitor and the

VDD & GND pins be minimized to reduce pin

inductance.

2. A ground plane is recommended to minimize

parasitic inductance and impedance of the return

paths. The MIC44F18 family of drivers is capable

of high peak currents and very fast transition

times. Any impedance between the driver, the

decoupling capacitors and the external MOSFET

will degrade the performance of the circuit.

3. Trace out the high di/dt and dv/dt paths, as shown

in Figures 7 and 8 and minimize etch length and

loop area for these connections. Minimizing these

parameters decreases the parasitic inductance

and the radiated EMI generated by fast rise and

fall times.

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