ADIS16365SLASHPCBZ datasheet(15/20 Pages) AD

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Preliminary Technical Data

ADIS16365

Rev. PrA | Page 15 of 20

Data-Ready I/O Indicator

The MSC_CTRL register provides controls for a data-ready

function. For example, writing 0x05 to this register enables this

function and establishes DIO2 as an active-low, data-ready line.

The duty cycle is 25% (±10% tolerance).

Table 17. MSC_CTRL Bit Descriptions

Bits

Description

(Default = 0x0000)

[15:12]

Not used

[11]

Flash test

[10]

Internal self-test enable (clears on completion)

1 = enabled, 0 = disabled

[9]

Manual self-test, negative stimulus

1 = enabled, 0 = disabled

[8]

Manual self-test, positive stimulus

1 = enabled, 0 = disabled

[7]

Linear acceleration bias compensation for gyroscopes

1 = enabled, 0 = disabled

[6]

Linear accelerometer origin alignment

1 = enabled, 0 = disabled

[5:3]

Not used

[2]

Data-ready enable, 1 = enabled, 0 = disabled

[1]

Data-ready polarity, 1 = active high, 0 = active low

[0]

Data-ready line select, 1 = DIO2, 0 = DIO1

General Purpose I/O

The GPIO_CTRL register controls the direction and data of the

general-purpose digital lines, DIO1 through DIO4. For example,

writing a 0x02 to the GPIO_CTRL register sets DIO2 as an

output line and DIO1, DIO3, and DIO4 as input lines. Reading

the data bits in GPIO_CTRL reveals the logic level of each line.

Table 18. GPIO_CTRL Bit Descriptions

Bit

Description

(Default = 0x0000)

[15:12]

Not used

[11]

General-Purpose I/O Line 4 data level

[10]

General-Purpose I/O Line 3 data level

[9]

General-Purpose I/O Line 2 data level

[8]

General-Purpose I/O Line 1 data level

[7:4]

Not used

[3]

General-Purpose I/O Line 4, data direction control

1 = output, 0 = input

[2]

General-Purpose I/O Line 3, data direction control

1 = output, 0 = input

[1]

General-Purpose I/O Line 2, data direction control

1 = output, 0 = input

[0]

General-Purpose I/O Line 1, data direction control

1 = output, 0 = input

DIAGNOSTICS

Self-Test

Self-test exercises the mechanical structure of the sensor and

provides a simple method for verifying the operation of the

entire sensor signal conditioning circuit. There are two different

self-test options: startup and manual. If either of these self-tests

results in a failure, the self-test error flag, located in the STATUS

repeating pattern, until the bit is set back to 0. While in the

manual self-test loop, SMPL_PRD and AVG_CNT cannot be

changed. See Table 17 for the appropriate MSC_CTRL bit

designations.

Alarm Registers

The alarm function provides monitoring for two independent

conditions. The ALM_CTRL register provides control inputs

for data source, data filtering (prior to comparison), static/

dynamic, and output indicator configurations. The ALM_MAGx

registers establish the trigger threshold and polarity configura-

tions. The ALM_SMPLx registers provide the numbers of

samples to use in the dynamic, rate-of-change configuration.

The rate-of-change calculation is

)

(

)

(

Alarm

⇒

−

∑

where:

NDS is the number of samples in ALM_SMPLx.

y(n) is the sampled output data.

MC is the magnitude for comparison in ALM_MAGx.

> or < is determined by the MSB in ALM_MAGx.

Table 19. ALM_MAG1/ALM_MAG2 Bit Designations

Bit

Description

(Default = 0x0000)

[15]

Comparison polarity: 1 = greater than, 0 = less than

[14]

Not used

[13:0]

Data bits, matches format of trigger source selection

Table 20. ALM_SMPL1/ALM_SMPL2 Bit Designations

Bit

Description

(Default = 0x0001)

[15:8]

Not used

[7:0]

Data bits: number of samples (both 0x00 and 0x01 = 1)

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